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mongoose / examples / NXP_K64 / clock_config.c @ eaef5bd1

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/* clang-format off */
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/*
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 * Copyright (c) 2015, Freescale Semiconductor, Inc.
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without modification,
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 * are permitted provided that the following conditions are met:
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 *
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 * o Redistributions of source code must retain the above copyright notice, this list
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 *   of conditions and the following disclaimer.
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 *
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 * o Redistributions in binary form must reproduce the above copyright notice, this
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 *   list of conditions and the following disclaimer in the documentation and/or
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 *   other materials provided with the distribution.
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 *
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 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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 *   contributors may be used to endorse or promote products derived from this
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 *   software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include "fsl_common.h"
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#include "fsl_smc.h"
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#include "clock_config.h"
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/*******************************************************************************
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 * Definitions
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 ******************************************************************************/
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/*! @brief Clock configuration structure. */
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typedef struct _clock_config
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{
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    mcg_config_t mcgConfig;       /*!< MCG configuration.      */
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    sim_clock_config_t simConfig; /*!< SIM configuration.      */
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    osc_config_t oscConfig;       /*!< OSC configuration.      */
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    uint32_t coreClock;           /*!< core clock frequency.   */
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} clock_config_t;
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/*******************************************************************************
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 * Variables
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 ******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/* Configuration for enter VLPR mode. Core clock = 4MHz. */
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const clock_config_t g_defaultClockConfigVlpr = {
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    .mcgConfig =
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        {
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            .mcgMode = kMCG_ModeBLPI,            /* Work in BLPI mode. */
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            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
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            .ircs = kMCG_IrcFast,                /* Select IRC4M. */
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            .fcrdiv = 0U,                        /* FCRDIV is 0. */
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            .frdiv = 0U,
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            .drs = kMCG_DrsLow,         /* Low frequency range. */
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            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
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            .oscsel = kMCG_OscselOsc,   /* Select OSC. */
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            .pll0Config =
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                {
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                    .enableMode = 0U, /* Don't eanble PLL. */
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                    .prdiv = 0U,
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                    .vdiv = 0U,
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                },
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        },
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    .simConfig =
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        {
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            .pllFllSel = 3U,        /* PLLFLLSEL select IRC48MCLK. */
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            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
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            .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
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        },
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    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
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                  .capLoad = 0,
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                  .workMode = kOSC_ModeExt,
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                  .oscerConfig =
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                      {
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                          .enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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                          .erclkDiv = 0U,
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#endif
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                      }},
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    .coreClock = 4000000U, /* Core clock frequency */
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};
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/* Configuration for enter RUN mode. Core clock = 120MHz. */
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const clock_config_t g_defaultClockConfigRun = {
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    .mcgConfig =
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        {
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            .mcgMode = kMCG_ModePEE,             /* Work in PEE mode. */
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            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
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            .ircs = kMCG_IrcSlow,                /* Select IRC32k. */
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            .fcrdiv = 0U,                        /* FCRDIV is 0. */
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            .frdiv = 7U,
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            .drs = kMCG_DrsLow,         /* Low frequency range. */
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            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
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            .oscsel = kMCG_OscselOsc,   /* Select OSC. */
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            .pll0Config =
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                {
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                    .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U,
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                },
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        },
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    .simConfig =
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        {
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            .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
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            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
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            .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
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        },
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    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
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                  .capLoad = 0,
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                  .workMode = kOSC_ModeExt,
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                  .oscerConfig =
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                      {
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                          .enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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                          .erclkDiv = 0U,
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#endif
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                      }},
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    .coreClock = 120000000U, /* Core clock frequency */
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};
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/*******************************************************************************
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 * Code
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 ******************************************************************************/
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/*
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 * How to setup clock using clock driver functions:
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 *
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 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
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 *    and flash clock are in allowed range during clock mode switch.
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 *
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 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
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 *
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 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
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 *    internal reference clock(MCGIRCLK). Follow the steps to setup:
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 *
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 *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
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 *
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 *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
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 *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
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 *        explicitly to setup MCGIRCLK.
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 *
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 *    3). Don't need to configure FLL explicitly, because if target mode is FLL
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 *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
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 *        if the target mode is not FLL mode, the FLL is disabled.
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 *
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 *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
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 *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
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 *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
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 *
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 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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 */
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void BOARD_BootClockVLPR(void)
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{
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    CLOCK_SetSimSafeDivs();
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    CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
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                         g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
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    CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
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    SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
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    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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    SMC_SetPowerModeVlpr(SMC, false);
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    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
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    {
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    }
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}
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void BOARD_BootClockRUN(void)
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{
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    CLOCK_SetSimSafeDivs();
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    CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
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    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
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    CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
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                        &g_defaultClockConfigRun.mcgConfig.pll0Config);
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    CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
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                                  g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
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    CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
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    SystemCoreClock = g_defaultClockConfigRun.coreClock;
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}