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/* clang-format off */
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/*******************************************************************************
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  MPLAB Harmony System Configuration Header
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  File Name:
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    system_config.h
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  Summary:
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    Build-time configuration header for the system defined by this MPLAB Harmony
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    project.
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  Description:
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    An MPLAB Project may have multiple configurations.  This file defines the
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    build-time options for a single configuration.
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  Remarks:
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    This configuration header must not define any prototypes or data
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    definitions (or include any files that do).  It only provides macro
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    definitions for build-time configuration options that are not instantiated
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    until used by another MPLAB Harmony module or application.
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    Created with MPLAB Harmony Version 1.09
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*******************************************************************************/
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// DOM-IGNORE-BEGIN
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/*******************************************************************************
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Copyright (c) 2013-2015 released Microchip Technology Inc.  All rights reserved.
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Microchip licenses to you the right to use, modify, copy and distribute
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Software only when embedded on a Microchip microcontroller or digital signal
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controller that is integrated into your product or third party product
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(pursuant to the sublicense terms in the accompanying license agreement).
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You should refer to the license agreement accompanying this Software for
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additional information regarding your rights and obligations.
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SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND,
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EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF
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MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE.
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IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER
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CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR
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OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES
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INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR
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CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF
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SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES
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(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
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*******************************************************************************/
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// DOM-IGNORE-END
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#ifndef _SYSTEM_CONFIG_H
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#define _SYSTEM_CONFIG_H
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// *****************************************************************************
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// *****************************************************************************
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// Section: Included Files
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// *****************************************************************************
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// *****************************************************************************
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/*  This section Includes other configuration headers necessary to completely
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    define this configuration.
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*/
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#include "bsp_config.h"
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// DOM-IGNORE-BEGIN
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#ifdef __cplusplus  // Provide C++ Compatibility
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extern "C" {
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#endif
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// DOM-IGNORE-END
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// *****************************************************************************
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// *****************************************************************************
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// Section: System Service Configuration
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// *****************************************************************************
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// *****************************************************************************
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// *****************************************************************************
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/* Common System Service Configuration Options
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*/
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#define SYS_VERSION_STR           "1.09"
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#define SYS_VERSION               10900
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// *****************************************************************************
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/* Clock System Service Configuration Options
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*/
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#define SYS_CLK_FREQ                        80000000ul
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#define SYS_CLK_BUS_PERIPHERAL_1            80000000ul
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#define SYS_CLK_UPLL_BEFORE_DIV2_FREQ       48000000ul
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#define SYS_CLK_CONFIG_PRIMARY_XTAL         8000000ul
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#define SYS_CLK_CONFIG_SECONDARY_XTAL       32768ul
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/*** Interrupt System Service Configuration ***/
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#define SYS_INT                     true
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/*** Ports System Service Configuration ***/
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#define SYS_PORT_AD1PCFG        ~0xffff
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#define SYS_PORT_CNPUE          0x0
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#define SYS_PORT_CNEN           0x0
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#define SYS_PORT_A_TRIS         0xc680
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#define SYS_PORT_A_LAT          0x0
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#define SYS_PORT_A_ODC          0x0
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#define SYS_PORT_B_TRIS         0x20
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#define SYS_PORT_B_LAT          0x0
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#define SYS_PORT_B_ODC          0x0
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/*** Timer System Service Configuration ***/
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#define SYS_TMR_POWER_STATE             SYS_MODULE_POWER_RUN_FULL
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#define SYS_TMR_DRIVER_INDEX            DRV_TMR_INDEX_0
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#define SYS_TMR_MAX_CLIENT_OBJECTS      5
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#define SYS_TMR_FREQUENCY               1000
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#define SYS_TMR_FREQUENCY_TOLERANCE     10
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#define SYS_TMR_UNIT_RESOLUTION         10000
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#define SYS_TMR_CLIENT_TOLERANCE        10
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#define SYS_TMR_INTERRUPT_NOTIFICATION  false
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/*** Console System Service Configuration ***/
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#define SYS_CONSOLE_OVERRIDE_STDIO
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#define SYS_CONSOLE_DEVICE_MAX_INSTANCES        2
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#define SYS_CONSOLE_INSTANCES_NUMBER            1
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#define SYS_CONSOLE_UART_IDX               DRV_USART_INDEX_0
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#define SYS_CONSOLE_UART_RD_QUEUE_DEPTH    1
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#define SYS_CONSOLE_UART_WR_QUEUE_DEPTH    64
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#define SYS_CONSOLE_BUFFER_DMA_READY
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/*** Debug System Service Configuration ***/
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#define SYS_DEBUG_ENABLE
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#define DEBUG_PRINT_BUFFER_SIZE       512
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#define SYS_DEBUG_BUFFER_DMA_READY
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#define SYS_DEBUG_USE_CONSOLE
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/*** Command Processor System Service Configuration ***/
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#define SYS_CMD_ENABLE
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#define SYS_CMD_DEVICE_MAX_INSTANCES    SYS_CONSOLE_DEVICE_MAX_INSTANCES
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#define SYS_CMD_PRINT_BUFFER_SIZE       512
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#define SYS_CMD_BUFFER_DMA_READY
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#define SYS_CMD_REMAP_SYS_CONSOLE_MESSAGE
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#define SYS_CMD_REMAP_SYS_DEBUG_MESSAGE
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// *****************************************************************************
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/* Random System Service Configuration Options
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*/
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#define SYS_RANDOM_CRYPTO_SEED_SIZE  32
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// *****************************************************************************
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// *****************************************************************************
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// Section: Driver Configuration
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// *****************************************************************************
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// *****************************************************************************
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/*** ENCX24J600 Driver Configuration ***/
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/*** Driver Compilation and static configuration options. ***/
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#define TCPIP_IF_ENCX24J600
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#define DRV_ENCX24J600_INSTANCES_NUMBER 1
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#define DRV_ENCX24J600_CLIENT_INSTANCES 1
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#define DRV_ENCX24J600_MAC_TX_DESCRIPTORS_IDX0 3
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#define DRV_ENCX24J600_MAC_RX_DESCRIPTORS_IDX0 3
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#define DRV_ENCX24J600_MAX_RX_BUFFER_IDX0 1536
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#define DRV_ENCX24J600_SPI_DRIVER_INDEX_IDX0 0
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#define DRV_ENCX24J600_SPI_BPS_IDX0 14000000
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#define DRV_ENCX24J600_SPI_SS_PORT_MODULE_IDX0 PORTS_ID_0
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#define DRV_ENCX24J600_SPI_SS_PORT_CHANNEL_IDX0 PORT_CHANNEL_D
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#define DRV_ENCX24J600_SPI_SS_PORT_PIN_IDX0 PORTS_BIT_POS_14
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#define DRV_ENCX24J600_RX_BUFFER_SIZE_IDX0 16384
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#define DRV_ENCX24J600_MAX_FRAME_SIZE_IDX0 1536
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/*** Timer Driver Configuration ***/
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#define DRV_TMR_INTERRUPT_MODE             true
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#define DRV_TMR_INSTANCES_NUMBER           1
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#define DRV_TMR_CLIENTS_NUMBER             1
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/*** Timer Driver 0 Configuration ***/
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#define DRV_TMR_PERIPHERAL_ID_IDX0          TMR_ID_1
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#define DRV_TMR_INTERRUPT_SOURCE_IDX0       INT_SOURCE_TIMER_1
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#define DRV_TMR_INTERRUPT_VECTOR_IDX0       INT_VECTOR_T1
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#define DRV_TMR_ISR_VECTOR_IDX0             _TIMER_1_VECTOR
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#define DRV_TMR_INTERRUPT_PRIORITY_IDX0     INT_PRIORITY_LEVEL1
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#define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0
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#define DRV_TMR_CLOCK_SOURCE_IDX0           DRV_TMR_CLKSOURCE_INTERNAL
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#define DRV_TMR_PRESCALE_IDX0               TMR_PRESCALE_VALUE_256
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#define DRV_TMR_OPERATION_MODE_IDX0         DRV_TMR_OPERATION_MODE_16_BIT
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#define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0     false
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#define DRV_TMR_POWER_STATE_IDX0            SYS_MODULE_POWER_RUN_FULL
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 // *****************************************************************************
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/* USART Driver Configuration Options
189
*/
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#define DRV_USART_INTERRUPT_MODE                    false
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#define DRV_USART_BYTE_MODEL_SUPPORT                false
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#define DRV_USART_READ_WRITE_MODEL_SUPPORT          true
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#define DRV_USART_BUFFER_QUEUE_SUPPORT              true
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#define DRV_USART_CLIENTS_NUMBER                    1
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#define DRV_USART_SUPPORT_TRANSMIT_DMA              false
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#define DRV_USART_SUPPORT_RECEIVE_DMA               false
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#define DRV_USART_INSTANCES_NUMBER                  1
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#define DRV_USART_PERIPHERAL_ID_IDX0                USART_ID_2
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#define DRV_USART_OPER_MODE_IDX0                    DRV_USART_OPERATION_MODE_NORMAL
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#define DRV_USART_OPER_MODE_DATA_IDX0
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#define DRV_USART_INIT_FLAG_WAKE_ON_START_IDX0      false
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#define DRV_USART_INIT_FLAG_AUTO_BAUD_IDX0          false
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#define DRV_USART_INIT_FLAG_STOP_IN_IDLE_IDX0       false
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#define DRV_USART_INIT_FLAGS_IDX0                   0
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#define DRV_USART_BRG_CLOCK_IDX0                    80000000
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#define DRV_USART_BAUD_RATE_IDX0                    115200
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#define DRV_USART_LINE_CNTRL_IDX0                   DRV_USART_LINE_CONTROL_8NONE1
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#define DRV_USART_HANDSHAKE_MODE_IDX0               DRV_USART_HANDSHAKE_NONE
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#define DRV_USART_XMIT_INT_SRC_IDX0                 INT_SOURCE_USART_2_TRANSMIT
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#define DRV_USART_RCV_INT_SRC_IDX0                  INT_SOURCE_USART_2_RECEIVE
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#define DRV_USART_ERR_INT_SRC_IDX0                  INT_SOURCE_USART_2_ERROR
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#define DRV_USART_XMIT_QUEUE_SIZE_IDX0              10
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#define DRV_USART_RCV_QUEUE_SIZE_IDX0               10
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#define DRV_USART_POWER_STATE_IDX0                  SYS_MODULE_POWER_RUN_FULL
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#define DRV_USART_QUEUE_DEPTH_COMBINED              20
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/*** SPI Driver Configuration ***/
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#define DRV_SPI_NUMBER_OF_MODULES                4
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/*** Driver Compilation and static configuration options. ***/
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/*** Select SPI compilation units.***/
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#define DRV_SPI_POLLED                                 0
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#define DRV_SPI_ISR                                 1
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#define DRV_SPI_MASTER                                 1
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#define DRV_SPI_SLAVE                                 0
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#define DRV_SPI_RM                                         0
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#define DRV_SPI_EBM                                 1
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#define DRV_SPI_8BIT                                 1
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#define DRV_SPI_16BIT                                 0
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#define DRV_SPI_32BIT                                 0
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#define DRV_SPI_DMA                                 0
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/*** SPI Driver Static Allocation Options ***/
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#define DRV_SPI_INSTANCES_NUMBER                 1
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#define DRV_SPI_CLIENTS_NUMBER                         1
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#define DRV_SPI_ELEMENTS_PER_QUEUE                 10
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/* SPI Driver Instance 0 Configuration */
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#define DRV_SPI_SPI_ID_IDX0                                 SPI_ID_1
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#define DRV_SPI_TASK_MODE_IDX0                                 DRV_SPI_TASK_MODE_ISR
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#define DRV_SPI_SPI_MODE_IDX0                                DRV_SPI_MODE_MASTER
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#define DRV_SPI_ALLOW_IDLE_RUN_IDX0                        false
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#define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0                 DRV_SPI_PROTOCOL_TYPE_STANDARD
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#define DRV_SPI_COMM_WIDTH_IDX0                         SPI_COMMUNICATION_WIDTH_8BITS
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#define DRV_SPI_SPI_CLOCK_IDX0                                 CLK_BUS_PERIPHERAL_2
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#define DRV_SPI_BAUD_RATE_IDX0                                 13333333
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#define DRV_SPI_BUFFER_TYPE_IDX0                         DRV_SPI_BUFFER_TYPE_ENHANCED
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#define DRV_SPI_CLOCK_MODE_IDX0                         DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL
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#define DRV_SPI_INPUT_PHASE_IDX0                         SPI_INPUT_SAMPLING_PHASE_AT_END
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#define DRV_SPI_TX_INT_SOURCE_IDX0                         INT_SOURCE_SPI_1_TRANSMIT
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#define DRV_SPI_RX_INT_SOURCE_IDX0                         INT_SOURCE_SPI_1_RECEIVE
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#define DRV_SPI_ERROR_INT_SOURCE_IDX0                 INT_SOURCE_SPI_1_ERROR
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#define DRV_SPI_INT_VECTOR_IDX0                                INT_VECTOR_SPI1
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#define DRV_SPI_INT_PRIORITY_IDX0                        INT_PRIORITY_LEVEL1
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#define DRV_SPI_INT_SUB_PRIORITY_IDX0                INT_SUBPRIORITY_LEVEL0
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#define DRV_SPI_QUEUE_SIZE_IDX0                         10
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#define DRV_SPI_RESERVED_JOB_IDX0                         1
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/*** ENCX24J600 Driver Configuration ***/
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/*** Driver Compilation and static configuration options. ***/
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#define TCPIP_IF_ENCX24J600
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#define DRV_ENCX24J600_INSTANCES_NUMBER 1
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#define DRV_ENCX24J600_CLIENT_INSTANCES 1
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#define DRV_ENCX24J600_MAC_TX_DESCRIPTORS_IDX0 3
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#define DRV_ENCX24J600_MAC_RX_DESCRIPTORS_IDX0 3
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#define DRV_ENCX24J600_MAX_RX_BUFFER_IDX0 1536
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#define DRV_ENCX24J600_SPI_DRIVER_INDEX_IDX0 0
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#define DRV_ENCX24J600_SPI_BPS_IDX0 14000000
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#define DRV_ENCX24J600_SPI_SS_PORT_MODULE_IDX0 PORTS_ID_0
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#define DRV_ENCX24J600_SPI_SS_PORT_CHANNEL_IDX0 PORT_CHANNEL_D
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#define DRV_ENCX24J600_SPI_SS_PORT_PIN_IDX0 PORTS_BIT_POS_14
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#define DRV_ENCX24J600_RX_BUFFER_SIZE_IDX0 16384
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#define DRV_ENCX24J600_MAX_FRAME_SIZE_IDX0 1536
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// *****************************************************************************
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// *****************************************************************************
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// Section: Middleware & Other Library Configuration
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// *****************************************************************************
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// *****************************************************************************
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// *****************************************************************************
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// *****************************************************************************
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// Section: TCPIP Stack Configuration
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// *****************************************************************************
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// *****************************************************************************
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#define TCPIP_STACK_USE_IPV4
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#define TCPIP_STACK_USE_TCP
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#define TCPIP_STACK_USE_UDP
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#define TCPIP_STACK_TICK_RATE                                        5
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#define TCPIP_STACK_SECURE_PORT_ENTRIES             10
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/* TCP/IP stack event notification */
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#define TCPIP_STACK_USE_EVENT_NOTIFICATION
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#define TCPIP_STACK_USER_NOTIFICATION   false
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#define TCPIP_STACK_DOWN_OPERATION   true
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#define TCPIP_STACK_IF_UP_DOWN_OPERATION   true
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#define TCPIP_STACK_MAC_DOWN_OPERATION  true
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#define TCPIP_STACK_CONFIGURATION_SAVE_RESTORE   true
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/*** TCPIP Heap Configuration ***/
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#define TCPIP_STACK_USE_INTERNAL_HEAP
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#define TCPIP_STACK_DRAM_SIZE                       39250
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#define TCPIP_STACK_DRAM_RUN_LIMIT                  2048
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#define TCPIP_STACK_MALLOC_FUNC                     malloc
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#define TCPIP_STACK_CALLOC_FUNC                     calloc
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#define TCPIP_STACK_FREE_FUNC                       free
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#define TCPIP_STACK_HEAP_USE_FLAGS                   TCPIP_STACK_HEAP_FLAG_ALLOC_UNCACHED
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#define TCPIP_STACK_HEAP_USAGE_CONFIG                TCPIP_STACK_HEAP_USE_DEFAULT
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#define TCPIP_STACK_SUPPORTED_HEAPS                  1
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/*** ARP Configuration ***/
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#define TCPIP_ARP_CACHE_ENTRIES                                 5
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#define TCPIP_ARP_CACHE_DELETE_OLD                                true
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#define TCPIP_ARP_CACHE_SOLVED_ENTRY_TMO                        1200
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#define TCPIP_ARP_CACHE_PENDING_ENTRY_TMO                        60
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#define TCPIP_ARP_CACHE_PENDING_RETRY_TMO                        2
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#define TCPIP_ARP_CACHE_PERMANENT_QUOTA                                    50
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#define TCPIP_ARP_CACHE_PURGE_THRESHOLD                                    75
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#define TCPIP_ARP_CACHE_PURGE_QUANTA                                    1
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#define TCPIP_ARP_CACHE_ENTRY_RETRIES                                    3
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#define TCPIP_ARP_GRATUITOUS_PROBE_COUNT                        1
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#define TCPIP_ARP_TASK_PROCESS_RATE                                2
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/*** DHCP Configuration ***/
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#define TCPIP_STACK_USE_DHCP_CLIENT
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#define TCPIP_DHCP_TIMEOUT                                        2
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#define TCPIP_DHCP_TASK_TICK_RATE                                    5
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#define TCPIP_DHCP_HOST_NAME_SIZE                                    20
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#define TCPIP_DHCP_CLIENT_CONNECT_PORT                          68
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#define TCPIP_DHCP_SERVER_LISTEN_PORT                                67
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#define TCPIP_DHCP_CLIENT_ENABLED                                     true
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/*** DNS Client Configuration ***/
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#define TCPIP_STACK_USE_DNS
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#define TCPIP_DNS_CLIENT_SERVER_TMO                                        60
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#define TCPIP_DNS_CLIENT_TASK_PROCESS_RATE                        200
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#define TCPIP_DNS_CLIENT_CACHE_ENTRIES                                5
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#define TCPIP_DNS_CLIENT_CACHE_ENTRY_TMO                        0
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#define TCPIP_DNS_CLIENT_CACHE_PER_IPV4_ADDRESS                5
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#define TCPIP_DNS_CLIENT_CACHE_PER_IPV6_ADDRESS                1
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#define TCPIP_DNS_CLIENT_ADDRESS_TYPE                            IP_ADDRESS_TYPE_IPV4
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#define TCPIP_DNS_CLIENT_CACHE_DEFAULT_TTL_VAL                1200
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#define TCPIP_DNS_CLIENT_CACHE_UNSOLVED_ENTRY_TMO        10
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#define TCPIP_DNS_CLIENT_LOOKUP_RETRY_TMO                        5
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#define TCPIP_DNS_CLIENT_MAX_HOSTNAME_LEN                        32
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#define TCPIP_DNS_CLIENT_MAX_SELECT_INTERFACES                4
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#define TCPIP_DNS_CLIENT_DELETE_OLD_ENTRIES                        true
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#define TCPIP_DNS_CLIENT_USER_NOTIFICATION   false
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/*** ICMPv4 Server Configuration ***/
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#define TCPIP_STACK_USE_ICMP_SERVER
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/*** NBNS Configuration ***/
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#define TCPIP_STACK_USE_NBNS
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#define TCPIP_NBNS_TASK_TICK_RATE   110
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/*** TCP Configuration ***/
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#define TCPIP_TCP_MAX_SEG_SIZE_TX                                1460
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#define TCPIP_TCP_MAX_SEG_SIZE_RX_LOCAL                                    1460
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#define TCPIP_TCP_MAX_SEG_SIZE_RX_NON_LOCAL                        536
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#define TCPIP_TCP_SOCKET_DEFAULT_TX_SIZE                        512
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#define TCPIP_TCP_SOCKET_DEFAULT_RX_SIZE                        512
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#define TCPIP_TCP_DYNAMIC_OPTIONS                                     true
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#define TCPIP_TCP_START_TIMEOUT_VAL                                1000
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#define TCPIP_TCP_DELAYED_ACK_TIMEOUT                                    100
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#define TCPIP_TCP_FIN_WAIT_2_TIMEOUT                                    5000
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#define TCPIP_TCP_KEEP_ALIVE_TIMEOUT                                    10000
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#define TCPIP_TCP_CLOSE_WAIT_TIMEOUT                                    200
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#define TCPIP_TCP_MAX_RETRIES                                            5
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#define TCPIP_TCP_MAX_UNACKED_KEEP_ALIVES                        6
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#define TCPIP_TCP_MAX_SYN_RETRIES                                3
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#define TCPIP_TCP_AUTO_TRANSMIT_TIMEOUT_VAL                        40
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#define TCPIP_TCP_WINDOW_UPDATE_TIMEOUT_VAL                        200
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#define TCPIP_TCP_MAX_SOCKETS                                10
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#define TCPIP_TCP_TASK_TICK_RATE                                5
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#define TCPIP_TCP_MSL_TIMEOUT                                    0
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#define TCPIP_TCP_QUIET_TIME                                    0
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/*** announce Configuration ***/
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#define TCPIP_STACK_USE_ANNOUNCE
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#define TCPIP_ANNOUNCE_MAX_PAYLOAD         512
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#define TCPIP_ANNOUNCE_TASK_RATE    333
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/*** TCPIP MAC Configuration ***/
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#define TCPIP_EMAC_TX_DESCRIPTORS                                8
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#define TCPIP_EMAC_RX_DESCRIPTORS                                6
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#define TCPIP_EMAC_RX_DEDICATED_BUFFERS                                4
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#define TCPIP_EMAC_RX_INIT_BUFFERS                                    0
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#define TCPIP_EMAC_RX_LOW_THRESHOLD                                    1
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#define TCPIP_EMAC_RX_LOW_FILL                                        2
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#define TCPIP_EMAC_RX_BUFF_SIZE                                            1536
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#define TCPIP_EMAC_RX_MAX_FRAME                                            1536
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#define TCPIP_EMAC_RX_FILTERS                       \
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                                                    TCPIP_MAC_RX_FILTER_TYPE_BCAST_ACCEPT |\
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                                                    TCPIP_MAC_RX_FILTER_TYPE_MCAST_ACCEPT |\
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                                                    TCPIP_MAC_RX_FILTER_TYPE_UCAST_ACCEPT |\
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                                                    TCPIP_MAC_RX_FILTER_TYPE_RUNT_REJECT |\
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                                                    TCPIP_MAC_RX_FILTER_TYPE_CRC_ERROR_REJECT |\
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                                                    0
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#define TCPIP_EMAC_RX_FRAGMENTS                                            1
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#define TCPIP_EMAC_ETH_OPEN_FLAGS                               \
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                                                    TCPIP_ETH_OPEN_AUTO |\
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                                                    TCPIP_ETH_OPEN_FDUPLEX |\
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                                                    TCPIP_ETH_OPEN_HDUPLEX |\
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                                                    TCPIP_ETH_OPEN_100 |\
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                                                    TCPIP_ETH_OPEN_10 |\
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                                                    TCPIP_ETH_OPEN_MDIX_AUTO |\
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                                                    0
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#define TCPIP_EMAC_PHY_CONFIG_FLAGS                             \
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                                                    DRV_ETHPHY_CFG_AUTO | \
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                                                    0
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#define TCPIP_EMAC_PHY_LINK_INIT_DELAY                          500
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#define TCPIP_EMAC_PHY_ADDRESS                                            0
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#define TCPIP_EMAC_MODULE_ID                                            ETH_ID_0
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#define TCPIP_EMAC_INTERRUPT_MODE                                true
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#define DRV_ETHPHY_INSTANCES_NUMBER                                1
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#define DRV_ETHPHY_CLIENTS_NUMBER                                1
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#define DRV_ETHPHY_INDEX                                        1
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#define DRV_ETHPHY_PERIPHERAL_ID                                1
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#define DRV_ETHPHY_NEG_INIT_TMO                                            1
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#define DRV_ETHPHY_NEG_DONE_TMO                                            2000
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#define DRV_ETHPHY_RESET_CLR_TMO                                500
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#define DRV_ETHMAC_INSTANCES_NUMBER                                1
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#define DRV_ETHMAC_CLIENTS_NUMBER                                1
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#define DRV_ETHMAC_INDEX                                                1
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#define DRV_ETHMAC_PERIPHERAL_ID                                1
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#define DRV_ETHMAC_INTERRUPT_VECTOR                                INT_VECTOR_ETHERNET
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#define DRV_ETHMAC_INTERRUPT_SOURCE                                INT_SOURCE_ETH_1
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#define DRV_ETHMAC_POWER_STATE                                            SYS_MODULE_POWER_RUN_FULL
459

    
460
#define DRV_ETHMAC_INTERRUPT_MODE                                true
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464
/*** UDP Configuration ***/
465
#define TCPIP_UDP_MAX_SOCKETS                                        10
466
#define TCPIP_UDP_SOCKET_DEFAULT_TX_SIZE                            512
467
#define TCPIP_UDP_SOCKET_DEFAULT_TX_QUEUE_LIMIT                     3
468
#define TCPIP_UDP_SOCKET_DEFAULT_RX_QUEUE_LIMIT                        3
469
#define TCPIP_UDP_USE_POOL_BUFFERS   false
470
#define TCPIP_UDP_USE_TX_CHECKSUM                                     true
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472
#define TCPIP_UDP_USE_RX_CHECKSUM                                     true
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474
#define TCPIP_STACK_USE_ZEROCONF_LINK_LOCAL
475
#define TCPIP_ZC_LL_PROBE_WAIT 1
476
#define TCPIP_ZC_LL_PROBE_MIN 1
477
#define TCPIP_ZC_LL_PROBE_MAX 2
478
#define TCPIP_ZC_LL_PROBE_NUM 3
479
#define TCPIP_ZC_LL_ANNOUNCE_WAIT 2
480
#define TCPIP_ZC_LL_ANNOUNCE_NUM 2
481
#define TCPIP_ZC_LL_ANNOUNCE_INTERVAL 2
482
#define TCPIP_ZC_LL_MAX_CONFLICTS 10
483
#define TCPIP_ZC_LL_RATE_LIMIT_INTERVAL 60
484
#define TCPIP_ZC_LL_DEFEND_INTERVAL 10
485
#define TCPIP_ZC_LL_IPV4_LLBASE 0xa9fe0100
486
#define TCPIP_ZC_LL_IPV4_LLBASE_MASK 0x0000FFFF
487
#define TCPIP_ZC_LL_TASK_TICK_RATE 333
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489
/*** Network Configuration Index 0 ***/
490
#define TCPIP_NETWORK_DEFAULT_INTERFACE_NAME                         "ENCX24J600"
491
#define TCPIP_NETWORK_DEFAULT_HOST_NAME                         "MCHPBOARD_E"
492
#define TCPIP_NETWORK_DEFAULT_MAC_ADDR                                 0
493
#define TCPIP_NETWORK_DEFAULT_IP_ADDRESS                         ""
494
#define TCPIP_NETWORK_DEFAULT_IP_MASK                                 "255.255.255.0"
495
#define TCPIP_NETWORK_DEFAULT_GATEWAY                                 ""
496
#define TCPIP_NETWORK_DEFAULT_DNS                                 ""
497
#define TCPIP_NETWORK_DEFAULT_SECOND_DNS                         "0.0.0.0"
498
#define TCPIP_NETWORK_DEFAULT_POWER_MODE                         "full"
499
#define TCPIP_NETWORK_DEFAULT_INTERFACE_FLAGS                       \
500
                                                    TCPIP_NETWORK_CONFIG_DHCP_CLIENT_ON |\
501
                                                    TCPIP_NETWORK_CONFIG_DNS_CLIENT_ON |\
502
                                                    TCPIP_NETWORK_CONFIG_IP_STATIC
503
#define TCPIP_NETWORK_DEFAULT_MAC_DRIVER                     DRV_ENCX24J600_MACObject
504
#define TCPIP_NETWORK_DEFAULT_IPV6_ADDRESS                         0
505
#define TCPIP_NETWORK_DEFAULT_IPV6_PREFIX_LENGTH    0
506
#define TCPIP_NETWORK_DEFAULT_IPV6_GATEWAY                     0
507
/*** tcpip_cmd Configuration ***/
508
#define TCPIP_STACK_COMMAND_ENABLE
509
#define TCPIP_STACK_COMMANDS_ICMP_ECHO_REQUESTS         4
510
#define TCPIP_STACK_COMMANDS_ICMP_ECHO_REQUEST_DELAY    1000
511
#define TCPIP_STACK_COMMANDS_ICMP_ECHO_TIMEOUT          5000
512
#define TCPIP_STACK_COMMANDS_WIFI_ENABLE                     false
513
#define TCPIP_STACK_COMMANDS_ICMP_ECHO_REQUEST_BUFF_SIZE    2000
514
#define TCPIP_STACK_COMMANDS_ICMP_ECHO_REQUEST_DATA_SIZE    100
515

    
516

    
517
/*** IPv4 Configuration ***/
518

    
519

    
520
// *****************************************************************************
521
/* BSP Configuration Options
522
*/
523
#define BSP_OSC_FREQUENCY 8000000
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527

    
528
// *****************************************************************************
529
// *****************************************************************************
530
// Section: Application Configuration
531
// *****************************************************************************
532
// *****************************************************************************
533

    
534
/*** Application Instance 0 Configuration ***/
535

    
536
//DOM-IGNORE-BEGIN
537
#ifdef __cplusplus
538
}
539
#endif
540
//DOM-IGNORE-END
541

    
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543
#endif // _SYSTEM_CONFIG_H
544
/*******************************************************************************
545
 End of File
546
*/
547