Revision 003243c3

View differences:

libavcodec/x86/vp8dsp-init.c
343 343
        c->vp8_v_loop_filter16y_inner = ff_vp8_v_loop_filter16y_inner_sse2;
344 344
        c->vp8_v_loop_filter8uv_inner = ff_vp8_v_loop_filter8uv_inner_sse2;
345 345

  
346
        c->vp8_v_loop_filter16y       = ff_vp8_v_loop_filter16y_mbedge_mmxext;
347
        c->vp8_v_loop_filter8uv       = ff_vp8_v_loop_filter8uv_mbedge_mmxext;
346
        c->vp8_v_loop_filter16y       = ff_vp8_v_loop_filter16y_mbedge_sse2;
347
        c->vp8_v_loop_filter8uv       = ff_vp8_v_loop_filter8uv_mbedge_sse2;
348 348
    }
349 349

  
350 350
    if (mm_flags & FF_MM_SSE2) {
351 351
        c->vp8_h_loop_filter16y_inner = ff_vp8_h_loop_filter16y_inner_sse2;
352 352
        c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_sse2;
353 353

  
354
        //c->vp8_h_loop_filter16y       = ff_vp8_h_loop_filter16y_mbedge_sse2;
355
        //c->vp8_h_loop_filter8uv       = ff_vp8_h_loop_filter8uv_mbedge_sse2;
354
        c->vp8_h_loop_filter16y       = ff_vp8_h_loop_filter16y_mbedge_sse2;
355
        c->vp8_h_loop_filter8uv       = ff_vp8_h_loop_filter8uv_mbedge_sse2;
356 356
    }
357 357

  
358 358
    if (mm_flags & FF_MM_SSSE3) {
......
372 372
        c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_ssse3;
373 373

  
374 374
        c->vp8_v_loop_filter16y       = ff_vp8_v_loop_filter16y_mbedge_ssse3;
375
        //c->vp8_h_loop_filter16y       = ff_vp8_h_loop_filter16y_mbedge_ssse3;
375
        c->vp8_h_loop_filter16y       = ff_vp8_h_loop_filter16y_mbedge_ssse3;
376 376
        c->vp8_v_loop_filter8uv       = ff_vp8_v_loop_filter8uv_mbedge_ssse3;
377
        //c->vp8_h_loop_filter8uv       = ff_vp8_h_loop_filter8uv_mbedge_ssse3;
377
        c->vp8_h_loop_filter8uv       = ff_vp8_h_loop_filter8uv_mbedge_ssse3;
378 378
    }
379 379

  
380 380
    if (mm_flags & FF_MM_SSE4) {
libavcodec/x86/vp8dsp.asm
2513 2513
%else ; sse2 (h)
2514 2514
    lea        dst8_reg, [dst8_reg+mstride_reg+1]
2515 2515
    WRITE_4x4D        1, 2, 3, 4, dst_reg, dst2_reg, dst8_reg, mstride_reg, stride_reg, %4
2516
    add         dst_reg, 4
2517
    add        dst8_reg, 4
2516
    lea         dst_reg, [dst2_reg+mstride_reg+4]
2517
    lea        dst8_reg, [dst8_reg+mstride_reg+4]
2518 2518
    WRITE_8W         m5, m5, dst2_reg, dst_reg,  mstride_reg, stride_reg
2519 2519
    WRITE_8W         m6, m6, dst2_reg, dst8_reg, mstride_reg, stride_reg
2520 2520
%endif

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