Revision 5137235e libavcodec/ppc/dsputil_altivec.c
| libavcodec/ppc/dsputil_altivec.c | ||
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include "config.h" |
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#if HAVE_ALTIVEC_H |
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#include <altivec.h> |
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#endif |
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#include "libavcodec/dsputil.h" |
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#include "gcc_fixes.h" |
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#include "dsputil_ppc.h" |
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#include "util_altivec.h" |
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#include "types_altivec.h" |
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static int hadamard8_diff16x8_altivec(/*MpegEncContext*/ void *s, uint8_t *dst, uint8_t *src, int stride, int h) {
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int sum; |
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register vector signed short |
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temp0 REG_v(v0),
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temp1 REG_v(v1),
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temp2 REG_v(v2),
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temp3 REG_v(v3),
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temp4 REG_v(v4),
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temp5 REG_v(v5),
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temp6 REG_v(v6),
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temp7 REG_v(v7);
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temp0 __asm__ ("v0"),
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temp1 __asm__ ("v1"),
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temp2 __asm__ ("v2"),
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temp3 __asm__ ("v3"),
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temp4 __asm__ ("v4"),
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temp5 __asm__ ("v5"),
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temp6 __asm__ ("v6"),
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temp7 __asm__ ("v7");
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register vector signed short |
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temp0S REG_v(v8),
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temp1S REG_v(v9),
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temp2S REG_v(v10),
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temp3S REG_v(v11),
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temp4S REG_v(v12),
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temp5S REG_v(v13),
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temp6S REG_v(v14),
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temp7S REG_v(v15);
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register const vector unsigned char vzero REG_v(v31)=
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temp0S __asm__ ("v8"),
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temp1S __asm__ ("v9"),
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temp2S __asm__ ("v10"),
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temp3S __asm__ ("v11"),
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temp4S __asm__ ("v12"),
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temp5S __asm__ ("v13"),
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temp6S __asm__ ("v14"),
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temp7S __asm__ ("v15");
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register const vector unsigned char vzero __asm__ ("v31") =
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(const vector unsigned char)vec_splat_u8(0); |
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{
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register const vector signed short vprod1 REG_v(v16)=
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register const vector signed short vprod1 __asm__ ("v16") =
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(const vector signed short){ 1,-1, 1,-1, 1,-1, 1,-1 };
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register const vector signed short vprod2 REG_v(v17)=
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register const vector signed short vprod2 __asm__ ("v17") =
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(const vector signed short){ 1, 1,-1,-1, 1, 1,-1,-1 };
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register const vector signed short vprod3 REG_v(v18)=
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register const vector signed short vprod3 __asm__ ("v18") =
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(const vector signed short){ 1, 1, 1, 1,-1,-1,-1,-1 };
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register const vector unsigned char perm1 REG_v(v19)=
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register const vector unsigned char perm1 __asm__ ("v19") =
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(const vector unsigned char) |
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{0x02, 0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05,
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0x0A, 0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D}; |
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register const vector unsigned char perm2 REG_v(v20)=
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register const vector unsigned char perm2 __asm__ ("v20") =
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(const vector unsigned char) |
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{0x04, 0x05, 0x06, 0x07, 0x00, 0x01, 0x02, 0x03,
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0x0C, 0x0D, 0x0E, 0x0F, 0x08, 0x09, 0x0A, 0x0B}; |
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register const vector unsigned char perm3 REG_v(v21)=
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register const vector unsigned char perm3 __asm__ ("v21") =
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(const vector unsigned char) |
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{0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; |
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#define ONEITERBUTTERFLY(i, res1, res2) \
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{ \
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register vector unsigned char src1 REG_v(v22), \
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src2 REG_v(v23), \
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dst1 REG_v(v24), \
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dst2 REG_v(v25), \
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srcO REG_v(v22), \
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dstO REG_v(v23); \
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#define ONEITERBUTTERFLY(i, res1, res2) \ |
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{ \
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register vector unsigned char src1 __asm__ ("v22"), \
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src2 __asm__ ("v23"), \
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dst1 __asm__ ("v24"), \
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dst2 __asm__ ("v25"), \
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srcO __asm__ ("v22"), \
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dstO __asm__ ("v23"); \
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\ |
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register vector signed short srcV REG_v(v24), \
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dstV REG_v(v25), \
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srcW REG_v(v26), \
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dstW REG_v(v27), \
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but0 REG_v(v28), \
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but0S REG_v(v29), \
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op1 REG_v(v30), \
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but1 REG_v(v22), \
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op1S REG_v(v23), \
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but1S REG_v(v24), \
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op2 REG_v(v25), \
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but2 REG_v(v26), \
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op2S REG_v(v27), \
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but2S REG_v(v28), \
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op3 REG_v(v29), \
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op3S REG_v(v30); \
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register vector signed short srcV __asm__ ("v24"), \
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dstV __asm__ ("v25"), \
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srcW __asm__ ("v26"), \
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dstW __asm__ ("v27"), \
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but0 __asm__ ("v28"), \
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but0S __asm__ ("v29"), \
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op1 __asm__ ("v30"), \
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but1 __asm__ ("v22"), \
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op1S __asm__ ("v23"), \
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but1S __asm__ ("v24"), \
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op2 __asm__ ("v25"), \
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but2 __asm__ ("v26"), \
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op2S __asm__ ("v27"), \
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but2S __asm__ ("v28"), \
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op3 __asm__ ("v29"), \
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op3S __asm__ ("v30"); \
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\ |
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src1 = vec_ld(stride * i, src); \ |
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src2 = vec_ld((stride * i) + 16, src); \ |
Also available in: Unified diff