Statistics
| Branch: | Revision:

ffmpeg / libavcodec / ppc / dsputil_ppc.c @ 5509bffa

History | View | Annotate | Download (10.4 KB)

1
/*
2
 * Copyright (c) 2002 Brian Foley
3
 * Copyright (c) 2002 Dieter Shirley
4
 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19
 */
20

    
21
#include "../dsputil.h"
22

    
23
#include "dsputil_ppc.h"
24

    
25
#ifdef HAVE_ALTIVEC
26
#include "dsputil_altivec.h"
27
#endif
28

    
29
extern void fdct_altivec(int16_t *block);
30
extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block);
31
extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block);
32

    
33
int mm_flags = 0;
34

    
35
int mm_support(void)
36
{
37
    int result = 0;
38
#ifdef HAVE_ALTIVEC
39
    if (has_altivec()) {
40
        result |= MM_ALTIVEC;
41
    }
42
#endif /* result */
43
    return result;
44
}
45

    
46
#ifdef POWERPC_PERFORMANCE_REPORT
47
unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total];
48
/* list below must match enum in dsputil_ppc.h */
49
static unsigned char* perfname[] = {
50
  "ff_fft_calc_altivec",
51
  "gmc1_altivec",
52
  "dct_unquantize_h263_altivec",
53
  "fdct_altivec",
54
  "idct_add_altivec",
55
  "idct_put_altivec",
56
  "put_pixels16_altivec",
57
  "avg_pixels16_altivec",
58
  "avg_pixels8_altivec",
59
  "put_pixels8_xy2_altivec",
60
  "put_no_rnd_pixels8_xy2_altivec",
61
  "put_pixels16_xy2_altivec",
62
  "put_no_rnd_pixels16_xy2_altivec",
63
  "hadamard8_diff8x8_altivec",
64
  "hadamard8_diff16_altivec",
65
  "avg_pixels8_xy2_altivec",
66
  "clear_blocks_dcbz32_ppc",
67
  "clear_blocks_dcbz128_ppc",
68
  "put_h264_chroma_mc8_altivec",
69
  "avg_h264_chroma_mc8_altivec",
70
  "put_h264_qpel16_h_lowpass_altivec",
71
  "avg_h264_qpel16_h_lowpass_altivec",
72
  "put_h264_qpel16_v_lowpass_altivec",
73
  "avg_h264_qpel16_v_lowpass_altivec",
74
  "put_h264_qpel16_hv_lowpass_altivec",
75
  "avg_h264_qpel16_hv_lowpass_altivec",
76
  ""
77
};
78
#include <stdio.h>
79
#endif
80

    
81
#ifdef POWERPC_PERFORMANCE_REPORT
82
void powerpc_display_perf_report(void)
83
{
84
  int i, j;
85
  av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
86
  for(i = 0 ; i < powerpc_perf_total ; i++)
87
  {
88
    for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++)
89
      {
90
        if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0)
91
          av_log(NULL, AV_LOG_INFO,
92
                  " Function \"%s\" (pmc%d):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
93
                  perfname[i],
94
                  j+1,
95
                  perfdata[j][i][powerpc_data_min],
96
                  perfdata[j][i][powerpc_data_max],
97
                  (double)perfdata[j][i][powerpc_data_sum] /
98
                  (double)perfdata[j][i][powerpc_data_num],
99
                  perfdata[j][i][powerpc_data_num]);
100
      }
101
  }
102
}
103
#endif /* POWERPC_PERFORMANCE_REPORT */
104

    
105
/* ***** WARNING ***** WARNING ***** WARNING ***** */
106
/*
107
  clear_blocks_dcbz32_ppc will not work properly
108
  on PowerPC processors with a cache line size
109
  not equal to 32 bytes.
110
  Fortunately all processor used by Apple up to
111
  at least the 7450 (aka second generation G4)
112
  use 32 bytes cache line.
113
  This is due to the use of the 'dcbz' instruction.
114
  It simply clear to zero a single cache line,
115
  so you need to know the cache line size to use it !
116
  It's absurd, but it's fast...
117

118
  update 24/06/2003 : Apple released yesterday the G5,
119
  with a PPC970. cache line size : 128 bytes. Oups.
120
  The semantic of dcbz was changed, it always clear
121
  32 bytes. so the function below will work, but will
122
  be slow. So I fixed check_dcbz_effect to use dcbzl,
123
  which is defined to clear a cache line (as dcbz before).
124
  So we still can distinguish, and use dcbz (32 bytes)
125
  or dcbzl (one cache line) as required.
126

127
  see <http://developer.apple.com/technotes/tn/tn2087.html>
128
  and <http://developer.apple.com/technotes/tn/tn2086.html>
129
*/
130
void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
131
{
132
POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1);
133
    register int misal = ((unsigned long)blocks & 0x00000010);
134
    register int i = 0;
135
POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
136
#if 1
137
    if (misal) {
138
      ((unsigned long*)blocks)[0] = 0L;
139
      ((unsigned long*)blocks)[1] = 0L;
140
      ((unsigned long*)blocks)[2] = 0L;
141
      ((unsigned long*)blocks)[3] = 0L;
142
      i += 16;
143
    }
144
    for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
145
#ifndef __MWERKS__
146
      asm volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
147
#else
148
      __dcbz( blocks, i );
149
#endif
150
    }
151
    if (misal) {
152
      ((unsigned long*)blocks)[188] = 0L;
153
      ((unsigned long*)blocks)[189] = 0L;
154
      ((unsigned long*)blocks)[190] = 0L;
155
      ((unsigned long*)blocks)[191] = 0L;
156
      i += 16;
157
    }
158
#else
159
    memset(blocks, 0, sizeof(DCTELEM)*6*64);
160
#endif
161
POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
162
}
163

    
164
/* same as above, when dcbzl clear a whole 128B cache line
165
   i.e. the PPC970 aka G5 */
166
#ifndef NO_DCBZL
167
void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
168
{
169
POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1);
170
    register int misal = ((unsigned long)blocks & 0x0000007f);
171
    register int i = 0;
172
POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
173
#if 1
174
 if (misal) {
175
   // we could probably also optimize this case,
176
   // but there's not much point as the machines
177
   // aren't available yet (2003-06-26)
178
      memset(blocks, 0, sizeof(DCTELEM)*6*64);
179
    }
180
    else
181
      for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
182
        asm volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
183
      }
184
#else
185
    memset(blocks, 0, sizeof(DCTELEM)*6*64);
186
#endif
187
POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
188
}
189
#else
190
void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
191
{
192
  memset(blocks, 0, sizeof(DCTELEM)*6*64);
193
}
194
#endif
195

    
196
#ifndef NO_DCBZL
197
/* check dcbz report how many bytes are set to 0 by dcbz */
198
/* update 24/06/2003 : replace dcbz by dcbzl to get
199
   the intended effect (Apple "fixed" dcbz)
200
   unfortunately this cannot be used unless the assembler
201
   knows about dcbzl ... */
202
long check_dcbzl_effect(void)
203
{
204
  register char *fakedata = (char*)av_malloc(1024);
205
  register char *fakedata_middle;
206
  register long zero = 0;
207
  register long i = 0;
208
  long count = 0;
209

    
210
  if (!fakedata)
211
  {
212
    return 0L;
213
  }
214

    
215
  fakedata_middle = (fakedata + 512);
216

    
217
  memset(fakedata, 0xFF, 1024);
218

    
219
  /* below the constraint "b" seems to mean "Address base register"
220
     in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
221
  asm volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
222

    
223
  for (i = 0; i < 1024 ; i ++)
224
  {
225
    if (fakedata[i] == (char)0)
226
      count++;
227
  }
228

    
229
  av_free(fakedata);
230

    
231
  return count;
232
}
233
#else
234
long check_dcbzl_effect(void)
235
{
236
  return 0;
237
}
238
#endif
239

    
240

    
241
void dsputil_h264_init_ppc(DSPContext* c, AVCodecContext *avctx);
242

    
243
void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
244
{
245
    // Common optimizations whether Altivec is available or not
246

    
247
  switch (check_dcbzl_effect()) {
248
  case 32:
249
    c->clear_blocks = clear_blocks_dcbz32_ppc;
250
    break;
251
  case 128:
252
    c->clear_blocks = clear_blocks_dcbz128_ppc;
253
    break;
254
  default:
255
    break;
256
  }
257

    
258
#ifdef HAVE_ALTIVEC
259
  dsputil_h264_init_ppc(c, avctx);
260

    
261
    if (has_altivec()) {
262
        mm_flags |= MM_ALTIVEC;
263

    
264
        // Altivec specific optimisations
265
        c->pix_abs[0][1] = sad16_x2_altivec;
266
        c->pix_abs[0][2] = sad16_y2_altivec;
267
        c->pix_abs[0][3] = sad16_xy2_altivec;
268
        c->pix_abs[0][0] = sad16_altivec;
269
        c->pix_abs[1][0] = sad8_altivec;
270
        c->sad[0]= sad16_altivec;
271
        c->sad[1]= sad8_altivec;
272
        c->pix_norm1 = pix_norm1_altivec;
273
        c->sse[1]= sse8_altivec;
274
        c->sse[0]= sse16_altivec;
275
        c->pix_sum = pix_sum_altivec;
276
        c->diff_pixels = diff_pixels_altivec;
277
        c->get_pixels = get_pixels_altivec;
278
// next one disabled as it's untested.
279
#if 0
280
        c->add_bytes= add_bytes_altivec;
281
#endif /* 0 */
282
        c->put_pixels_tab[0][0] = put_pixels16_altivec;
283
        /* the two functions do the same thing, so use the same code */
284
        c->put_no_rnd_pixels_tab[0][0] = put_pixels16_altivec;
285
        c->avg_pixels_tab[0][0] = avg_pixels16_altivec;
286
        c->avg_pixels_tab[1][0] = avg_pixels8_altivec;
287
        c->avg_pixels_tab[1][3] = avg_pixels8_xy2_altivec;
288
        c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec;
289
        c->put_no_rnd_pixels_tab[1][3] = put_no_rnd_pixels8_xy2_altivec;
290
        c->put_pixels_tab[0][3] = put_pixels16_xy2_altivec;
291
        c->put_no_rnd_pixels_tab[0][3] = put_no_rnd_pixels16_xy2_altivec;
292

    
293
        c->gmc1 = gmc1_altivec;
294

    
295
#ifdef CONFIG_DARWIN // ATM gcc-3.3 and gcc-3.4 fail to compile these in linux...
296
        c->hadamard8_diff[0] = hadamard8_diff16_altivec;
297
        c->hadamard8_diff[1] = hadamard8_diff8x8_altivec;
298
#endif
299

    
300
#ifdef CONFIG_ENCODERS
301
        if (avctx->dct_algo == FF_DCT_AUTO ||
302
            avctx->dct_algo == FF_DCT_ALTIVEC)
303
        {
304
            c->fdct = fdct_altivec;
305
        }
306
#endif //CONFIG_ENCODERS
307

    
308
      if (avctx->lowres==0)
309
      {
310
        if ((avctx->idct_algo == FF_IDCT_AUTO) ||
311
                (avctx->idct_algo == FF_IDCT_ALTIVEC))
312
        {
313
            c->idct_put = idct_put_altivec;
314
            c->idct_add = idct_add_altivec;
315
#ifndef ALTIVEC_USE_REFERENCE_C_CODE
316
            c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
317
#else /* ALTIVEC_USE_REFERENCE_C_CODE */
318
            c->idct_permutation_type = FF_NO_IDCT_PERM;
319
#endif /* ALTIVEC_USE_REFERENCE_C_CODE */
320
        }
321
      }
322

    
323
#ifdef POWERPC_PERFORMANCE_REPORT
324
        {
325
          int i, j;
326
          for (i = 0 ; i < powerpc_perf_total ; i++)
327
          {
328
            for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++)
329
              {
330
                perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL;
331
                perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL;
332
                perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL;
333
                perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL;
334
              }
335
          }
336
        }
337
#endif /* POWERPC_PERFORMANCE_REPORT */
338
    } else
339
#endif /* HAVE_ALTIVEC */
340
    {
341
        // Non-AltiVec PPC optimisations
342

    
343
        // ... pending ...
344
    }
345
}