ffmpeg / libavcodec / armv4l / dsputil_neon_s.S @ 569f5a75
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/* |
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* ARM NEON optimised DSP functions |
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com> |
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* |
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* This file is part of FFmpeg. |
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* |
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* FFmpeg is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* FFmpeg is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with FFmpeg; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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|
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#include "asm.S" |
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|
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preserve8 |
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.fpu neon |
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.text |
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|
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.macro pixels16 avg=0 |
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.if \avg |
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mov ip, r0 |
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.endif |
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1: vld1.64 {d0, d1}, [r1], r2
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vld1.64 {d2, d3}, [r1], r2
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vld1.64 {d4, d5}, [r1], r2
|
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pld [r1, r2, lsl #2] |
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vld1.64 {d6, d7}, [r1], r2
|
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pld [r1] |
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pld [r1, r2] |
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pld [r1, r2, lsl #1] |
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.if \avg |
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vld1.64 {d16,d17}, [ip], r2
|
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vrhadd.u8 q0, q0, q8 |
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vld1.64 {d18,d19}, [ip], r2
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vrhadd.u8 q1, q1, q9 |
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vld1.64 {d20,d21}, [ip], r2
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vrhadd.u8 q2, q2, q10 |
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vld1.64 {d22,d23}, [ip], r2
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vrhadd.u8 q3, q3, q11 |
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.endif |
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subs r3, r3, #4 |
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vst1.64 {d0, d1}, [r0,:128], r2
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vst1.64 {d2, d3}, [r0,:128], r2
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vst1.64 {d4, d5}, [r0,:128], r2
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vst1.64 {d6, d7}, [r0,:128], r2
|
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bne 1b |
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bx lr |
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.endm |
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|
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.macro pixels16_x2 vhadd=vrhadd.u8 |
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1: vld1.64 {d0-d2}, [r1], r2
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vld1.64 {d4-d6}, [r1], r2
|
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pld [r1] |
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pld [r1, r2] |
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subs r3, r3, #2 |
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vext.8 q1, q0, q1, #1 |
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\vhadd q0, q0, q1 |
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vext.8 q3, q2, q3, #1 |
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\vhadd q2, q2, q3 |
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vst1.64 {d0, d1}, [r0,:128], r2
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vst1.64 {d4, d5}, [r0,:128], r2
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bne 1b |
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bx lr |
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.endm |
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|
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.macro pixels16_y2 vhadd=vrhadd.u8 |
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push {lr}
|
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add ip, r1, r2 |
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lsl lr, r2, #1 |
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vld1.64 {d0, d1}, [r1], lr
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vld1.64 {d2, d3}, [ip], lr
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1: subs r3, r3, #2 |
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\vhadd q2, q0, q1 |
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vld1.64 {d0, d1}, [r1], lr
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\vhadd q3, q0, q1 |
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vld1.64 {d2, d3}, [ip], lr
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pld [r1] |
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pld [ip] |
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vst1.64 {d4, d5}, [r0,:128], r2
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vst1.64 {d6, d7}, [r0,:128], r2
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bne 1b |
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pop {pc}
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.endm |
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|
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.macro pixels16_xy2 vshrn=vrshrn.u16 no_rnd=0 |
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push {lr}
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lsl lr, r2, #1 |
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add ip, r1, r2 |
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vld1.64 {d0-d2}, [r1], lr
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vld1.64 {d4-d6}, [ip], lr
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.if \no_rnd |
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vmov.i16 q13, #1 |
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.endif |
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pld [r1] |
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pld [ip] |
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vext.8 q1, q0, q1, #1 |
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vext.8 q3, q2, q3, #1 |
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vaddl.u8 q8, d0, d2 |
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vaddl.u8 q10, d1, d3 |
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vaddl.u8 q9, d4, d6 |
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vaddl.u8 q11, d5, d7 |
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1: subs r3, r3, #2 |
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vld1.64 {d0-d2}, [r1], lr
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vadd.u16 q12, q8, q9 |
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pld [r1] |
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.if \no_rnd |
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vadd.u16 q12, q12, q13 |
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.endif |
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vext.8 q15, q0, q1, #1 |
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vadd.u16 q1 , q10, q11 |
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\vshrn d28, q12, #2 |
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.if \no_rnd |
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vadd.u16 q1, q1, q13 |
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.endif |
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\vshrn d29, q1, #2 |
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vaddl.u8 q8, d0, d30 |
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vld1.64 {d2-d4}, [ip], lr
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vaddl.u8 q10, d1, d31 |
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vst1.64 {d28,d29}, [r0,:128], r2
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vadd.u16 q12, q8, q9 |
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pld [ip] |
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.if \no_rnd |
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vadd.u16 q12, q12, q13 |
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.endif |
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vext.8 q2, q1, q2, #1 |
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vadd.u16 q0, q10, q11 |
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\vshrn d30, q12, #2 |
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.if \no_rnd |
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vadd.u16 q0, q0, q13 |
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.endif |
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\vshrn d31, q0, #2 |
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vaddl.u8 q9, d2, d4 |
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vaddl.u8 q11, d3, d5 |
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vst1.64 {d30,d31}, [r0,:128], r2
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bgt 1b |
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pop {pc}
|
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.endm |
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|
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.macro pixels8 |
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1: vld1.64 {d0}, [r1], r2
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vld1.64 {d1}, [r1], r2
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vld1.64 {d2}, [r1], r2
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pld [r1, r2, lsl #2] |
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vld1.64 {d3}, [r1], r2
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pld [r1] |
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pld [r1, r2] |
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pld [r1, r2, lsl #1] |
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subs r3, r3, #4 |
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vst1.64 {d0}, [r0,:64], r2
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vst1.64 {d1}, [r0,:64], r2
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vst1.64 {d2}, [r0,:64], r2
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vst1.64 {d3}, [r0,:64], r2
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bne 1b |
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bx lr |
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.endm |
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|
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.macro pixels8_x2 vhadd=vrhadd.u8 |
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1: vld1.64 {d0, d1}, [r1], r2
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vext.8 d1, d0, d1, #1 |
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vld1.64 {d2, d3}, [r1], r2
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vext.8 d3, d2, d3, #1 |
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pld [r1] |
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pld [r1, r2] |
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subs r3, r3, #2 |
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vswp d1, d2 |
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\vhadd q0, q0, q1 |
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vst1.64 {d0}, [r0,:64], r2
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vst1.64 {d1}, [r0,:64], r2
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bne 1b |
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bx lr |
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.endm |
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|
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.macro pixels8_y2 vhadd=vrhadd.u8 |
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push {lr}
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add ip, r1, r2 |
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lsl lr, r2, #1 |
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vld1.64 {d0}, [r1], lr
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vld1.64 {d1}, [ip], lr
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1: subs r3, r3, #2 |
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\vhadd d4, d0, d1 |
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vld1.64 {d0}, [r1], lr
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\vhadd d5, d0, d1 |
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vld1.64 {d1}, [ip], lr
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pld [r1] |
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pld [ip] |
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vst1.64 {d4}, [r0,:64], r2
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vst1.64 {d5}, [r0,:64], r2
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bne 1b |
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pop {pc}
|
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.endm |
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|
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.macro pixels8_xy2 vshrn=vrshrn.u16 no_rnd=0 |
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push {lr}
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lsl lr, r2, #1 |
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add ip, r1, r2 |
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vld1.64 {d0, d1}, [r1], lr
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vld1.64 {d2, d3}, [ip], lr
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.if \no_rnd |
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vmov.i16 q11, #1 |
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.endif |
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pld [r1] |
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pld [ip] |
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vext.8 d4, d0, d1, #1 |
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vext.8 d6, d2, d3, #1 |
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vaddl.u8 q8, d0, d4 |
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vaddl.u8 q9, d2, d6 |
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1: subs r3, r3, #2 |
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vld1.64 {d0, d1}, [r1], lr
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pld [r1] |
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vadd.u16 q10, q8, q9 |
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vext.8 d4, d0, d1, #1 |
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.if \no_rnd |
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vadd.u16 q10, q10, q11 |
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.endif |
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vaddl.u8 q8, d0, d4 |
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\vshrn d5, q10, #2 |
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vld1.64 {d2, d3}, [ip], lr
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vadd.u16 q10, q8, q9 |
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pld [ip] |
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.if \no_rnd |
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vadd.u16 q10, q10, q11 |
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.endif |
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vst1.64 {d5}, [r0,:64], r2
|
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\vshrn d7, q10, #2 |
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vext.8 d6, d2, d3, #1 |
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vaddl.u8 q9, d2, d6 |
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vst1.64 {d7}, [r0,:64], r2
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bgt 1b |
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pop {pc}
|
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.endm |
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|
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.macro pixfunc pfx name suf rnd_op args:vararg |
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function ff_\pfx\name\suf\()_neon, export=1 |
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\name \rnd_op \args |
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.endfunc |
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.endm |
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|
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.macro pixfunc2 pfx name args:vararg |
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pixfunc \pfx \name |
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pixfunc \pfx \name \args |
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.endm |
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|
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function ff_put_h264_qpel16_mc00_neon, export=1 |
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mov r3, #16 |
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.endfunc |
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|
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pixfunc put_ pixels16 |
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pixfunc2 put_ pixels16_x2, _no_rnd, vhadd.u8 |
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pixfunc2 put_ pixels16_y2, _no_rnd, vhadd.u8 |
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pixfunc2 put_ pixels16_xy2, _no_rnd, vshrn.u16, 1 |
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|
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function ff_avg_h264_qpel16_mc00_neon, export=1 |
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mov r3, #16 |
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.endfunc |
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|
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pixfunc avg_ pixels16,, 1 |
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|
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function ff_put_h264_qpel8_mc00_neon, export=1 |
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mov r3, #8 |
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.endfunc |
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|
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pixfunc put_ pixels8 |
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pixfunc2 put_ pixels8_x2, _no_rnd, vhadd.u8 |
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pixfunc2 put_ pixels8_y2, _no_rnd, vhadd.u8 |
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pixfunc2 put_ pixels8_xy2, _no_rnd, vshrn.u16, 1 |