Revision 6d606c4f postproc/swscale_template.c

View differences:

postproc/swscale_template.c
2271 2271
			PREFETCH" 32(%%"REG_c")		\n\t"
2272 2272
			PREFETCH" 64(%%"REG_c")		\n\t"
2273 2273

  
2274
#ifdef ARCH_X86_64
2275

  
2276
#define FUNNY_Y_CODE \
2277
			"movl (%%"REG_b"), %%esi	\n\t"\
2278
			"call *%4			\n\t"\
2279
			"movl (%%"REG_b", %%"REG_a"), %%esi\n\t"\
2280
			"add %%"REG_S", %%"REG_c"	\n\t"\
2281
			"add %%"REG_a", %%"REG_D"	\n\t"\
2282
			"xor %%"REG_a", %%"REG_a"	\n\t"\
2283

  
2284
#else
2285

  
2274 2286
#define FUNNY_Y_CODE \
2275
			"mov (%%"REG_b"), %%"REG_S"	\n\t"\
2287
			"movl (%%"REG_b"), %%esi	\n\t"\
2276 2288
			"call *%4			\n\t"\
2277
			"addl (%%"REG_b", %%"REG_a"), %%ecx\n\t"\
2289
			"addl (%%"REG_b", %%"REG_a"), %%"REG_c"\n\t"\
2278 2290
			"add %%"REG_a", %%"REG_D"	\n\t"\
2279 2291
			"xor %%"REG_a", %%"REG_a"	\n\t"\
2280 2292

  
2293
#endif
2294

  
2281 2295
FUNNY_Y_CODE
2282 2296
FUNNY_Y_CODE
2283 2297
FUNNY_Y_CODE
......
2440 2454
			PREFETCH" 32(%%"REG_c")		\n\t"
2441 2455
			PREFETCH" 64(%%"REG_c")		\n\t"
2442 2456

  
2457
#ifdef ARCH_X86_64
2458

  
2459
#define FUNNY_UV_CODE \
2460
			"movl (%%"REG_b"), %%esi	\n\t"\
2461
			"call *%4			\n\t"\
2462
			"movl (%%"REG_b", %%"REG_a"), %%esi\n\t"\
2463
			"add %%"REG_S", %%"REG_c"	\n\t"\
2464
			"add %%"REG_a", %%"REG_D"	\n\t"\
2465
			"xor %%"REG_a", %%"REG_a"	\n\t"\
2466

  
2467
#else
2468

  
2443 2469
#define FUNNY_UV_CODE \
2444 2470
			"movl (%%"REG_b"), %%esi	\n\t"\
2445 2471
			"call *%4			\n\t"\
2446
			"addl (%%"REG_b", %%"REG_a"), %%ecx\n\t"\
2472
			"addl (%%"REG_b", %%"REG_a"), %%"REG_c"\n\t"\
2447 2473
			"add %%"REG_a", %%"REG_D"	\n\t"\
2448 2474
			"xor %%"REG_a", %%"REG_a"	\n\t"\
2449 2475

  
2476
#endif
2477

  
2450 2478
FUNNY_UV_CODE
2451 2479
FUNNY_UV_CODE
2452 2480
FUNNY_UV_CODE
......
2466 2494

  
2467 2495
			:: "m" (src1), "m" (dst), "m" (mmx2Filter), "m" (mmx2FilterPos),
2468 2496
			"m" (funnyUVCode), "m" (src2)
2469
			: "%"REG_a, "%"REG_b, "%"REG_c, "%"REG_d, "%esi", "%"REG_D
2497
			: "%"REG_a, "%"REG_b, "%"REG_c, "%"REG_d, "%"REG_S, "%"REG_D
2470 2498
		);
2471 2499
		for(i=dstWidth-1; (i*xInc)>>16 >=srcW-1; i--)
2472 2500
		{

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