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ffmpeg / libavcodec / arm / mdct_neon.S @ 750f5034

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/*
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 * ARM NEON optimised MDCT
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 * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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 *
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 * This file is part of FFmpeg.
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 *
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 * FFmpeg is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
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 *
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 * FFmpeg is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with FFmpeg; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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 */
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#include "asm.S"
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        .fpu neon
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        .text
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function ff_imdct_half_neon, export=1
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        push            {r4-r8,lr}
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        mov             r12, #1
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        ldr             lr,  [r0, #4]           @ nbits
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        ldr             r4,  [r0, #8]           @ tcos
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        ldr             r5,  [r0, #12]          @ tsin
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        ldr             r3,  [r0, #24]          @ revtab
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        lsl             r12, r12, lr            @ n  = 1 << nbits
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        lsr             lr,  r12, #2            @ n4 = n >> 2
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        add             r7,  r2,  r12,  lsl #1
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        mov             r12,  #-16
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        sub             r7,  r7,  #16
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        vld2.32         {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0
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        vld2.32         {d0-d1},  [r2,:128]!    @ d0 =m0,x d1 =m1,x
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        vrev64.32       d17, d17
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        vld1.32         {d2},     [r4,:64]!     @ d2=c0,c1
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        vmul.f32        d6,  d17, d2
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        vld1.32         {d3},     [r5,:64]!     @ d3=s0,s1
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        vmul.f32        d7,  d0,  d2
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1:
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        subs            lr,  lr,  #2
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        ldr             r6,  [r3], #4
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        vmul.f32        d4,  d0,  d3
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        vmul.f32        d5,  d17, d3
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        vsub.f32        d4,  d6,  d4
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        vadd.f32        d5,  d5,  d7
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        uxtah           r8,  r1,  r6,  ror #16
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        uxtah           r6,  r1,  r6
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        beq             1f
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        vld2.32         {d16-d17},[r7,:128],r12
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        vld2.32         {d0-d1},  [r2,:128]!
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        vrev64.32       d17, d17
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        vld1.32         {d2},     [r4,:64]!
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        vmul.f32        d6,  d17, d2
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        vld1.32         {d3},     [r5,:64]!
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        vmul.f32        d7,  d0,  d2
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        vst2.32         {d4[0],d5[0]}, [r6,:64]
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        vst2.32         {d4[1],d5[1]}, [r8,:64]
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        b               1b
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1:
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        vst2.32         {d4[0],d5[0]}, [r6,:64]
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        vst2.32         {d4[1],d5[1]}, [r8,:64]
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        mov             r4,  r0
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        mov             r6,  r1
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        add             r0,  r0,  #16
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        bl              ff_fft_calc_neon
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        mov             r12, #1
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        ldr             lr,  [r4, #4]           @ nbits
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        ldr             r5,  [r4, #12]          @ tsin
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        ldr             r4,  [r4, #8]           @ tcos
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        lsl             r12, r12, lr            @ n  = 1 << nbits
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        lsr             lr,  r12, #3            @ n8 = n >> 3
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        add             r4,  r4,  lr,  lsl #2
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        add             r5,  r5,  lr,  lsl #2
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        add             r6,  r6,  lr,  lsl #3
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        sub             r1,  r4,  #8
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        sub             r2,  r5,  #8
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        sub             r3,  r6,  #16
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        mov             r7,  #-16
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        mov             r12, #-8
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        mov             r8,  r6
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        mov             r0,  r3
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        vld2.32         {d0-d1},  [r3,:128], r7 @ d0 =i1,r1 d1 =i0,r0
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        vld2.32         {d20-d21},[r6,:128]!    @ d20=i2,r2 d21=i3,r3
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        vld1.32         {d18},    [r2,:64], r12 @ d18=s1,s0
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1:
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        subs            lr,  lr,  #2
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        vmul.f32        d7,  d0,  d18
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        vld1.32         {d19},    [r5,:64]!     @ d19=s2,s3
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        vmul.f32        d4,  d1,  d18
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        vld1.32         {d16},    [r1,:64], r12 @ d16=c1,c0
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        vmul.f32        d5,  d21, d19
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        vld1.32         {d17},    [r4,:64]!     @ d17=c2,c3
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        vmul.f32        d6,  d20, d19
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        vmul.f32        d22, d1,  d16
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        vmul.f32        d23, d21, d17
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        vmul.f32        d24, d0,  d16
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        vmul.f32        d25, d20, d17
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        vadd.f32        d7,  d7,  d22
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        vadd.f32        d6,  d6,  d23
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        vsub.f32        d4,  d4,  d24
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        vsub.f32        d5,  d5,  d25
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        beq             1f
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        vld2.32         {d0-d1},  [r3,:128], r7
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        vld2.32         {d20-d21},[r6,:128]!
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        vld1.32         {d18},    [r2,:64], r12
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        vrev64.32       q3,  q3
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        vst2.32         {d4,d6},  [r0,:128], r7
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        vst2.32         {d5,d7},  [r8,:128]!
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        b               1b
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1:
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        vrev64.32       q3,  q3
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        vst2.32         {d4,d6},  [r0,:128]
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        vst2.32         {d5,d7},  [r8,:128]
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        pop             {r4-r8,pc}
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.endfunc
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function ff_imdct_calc_neon, export=1
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        push            {r4-r6,lr}
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        ldr             r3,  [r0, #4]
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        mov             r4,  #1
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        mov             r5,  r1
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        lsl             r4,  r4,  r3
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        add             r1,  r1,  r4
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        bl              ff_imdct_half_neon
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        add             r0,  r5,  r4,  lsl #2
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        add             r1,  r5,  r4,  lsl #1
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        sub             r0,  r0,  #8
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        sub             r2,  r1,  #16
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        mov             r3,  #-16
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        mov             r6,  #-8
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        vmov.i32        d30, #1<<31
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        vld1.32         {d0-d1},  [r2,:128], r3
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        pld             [r0, #-16]
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        vrev64.32       q0,  q0
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        vld1.32         {d2-d3},  [r1,:128]!
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        veor            d4,  d1,  d30
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        pld             [r2, #-16]
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        vrev64.32       q1,  q1
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        veor            d5,  d0,  d30
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        vst1.32         {d2},     [r0,:64], r6
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        vst1.32         {d3},     [r0,:64], r6
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        vst1.32         {d4-d5},  [r5,:128]!
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        subs            r4,  r4,  #16
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        bgt             1b
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        pop             {r4-r6,pc}
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.endfunc