Revision 7cebed70 libpostproc/postprocess_template.c

View differences:

libpostproc/postprocess_template.c
158 158
        "movd %%mm4, %1                         \n\t"
159 159

  
160 160
        : "=r" (numEq), "=r" (dcOk)
161
        : "r" (src), "r" ((long)stride), "m" (c->pQPb)
161
        : "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb)
162 162
        : "%"REG_a
163 163
        );
164 164

  
......
303 303
        "sub %1, %0                             \n\t"
304 304

  
305 305
        :
306
        : "r" (src), "r" ((long)stride), "m" (c->pQPb)
306
        : "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb)
307 307
        : "%"REG_a, "%"REG_c
308 308
    );
309 309
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
423 423
        "movq %%mm2, (%%"REG_c", %1)            \n\t"
424 424

  
425 425
        :
426
        : "r" (src), "r" ((long)stride)
426
        : "r" (src), "r" ((x86_reg)stride)
427 427
        : "%"REG_a, "%"REG_c
428 428
    );
429 429
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
545 545
        "movq %%mm0, (%%"REG_c", %1, 2)         \n\t" // line 7
546 546

  
547 547
        :
548
        : "r" (src), "r" ((long)stride), "m" (co->pQPb)
548
        : "r" (src), "r" ((x86_reg)stride), "m" (co->pQPb)
549 549
        : "%"REG_a, "%"REG_c
550 550
    );
551 551
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
810 810
        "movq %%mm2, (%0, %1, 4)                \n\t"
811 811

  
812 812
        :
813
        : "r" (src), "r" ((long)stride), "m" (c->pQPb)
813
        : "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb)
814 814
        : "%"REG_a, "%"REG_c
815 815
    );
816 816

  
......
1098 1098
        "movq %%mm0, (%0, %1)                   \n\t"
1099 1099

  
1100 1100
        : "+r" (src)
1101
        : "r" ((long)stride), "m" (c->pQPb)
1101
        : "r" ((x86_reg)stride), "m" (c->pQPb)
1102 1102
        : "%"REG_a, "%"REG_c
1103 1103
    );
1104 1104
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
1367 1367
DERING_CORE((%0, %1, 8)    ,(%%REGd, %1, 4),%%mm2,%%mm4,%%mm0,%%mm3,%%mm5,%%mm1,%%mm6,%%mm7)
1368 1368

  
1369 1369
        "1:                        \n\t"
1370
        : : "r" (src), "r" ((long)stride), "m" (c->pQPb), "m"(c->pQPb2)
1370
        : : "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb), "m"(c->pQPb2)
1371 1371
        : "%"REG_a, "%"REG_d, "%"REG_c
1372 1372
    );
1373 1373
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
1521 1521
        PAVGB(%%mm0, %%mm1)
1522 1522
        "movq %%mm1, (%%"REG_c", %1, 2)         \n\t"
1523 1523

  
1524
        : : "r" (src), "r" ((long)stride)
1524
        : : "r" (src), "r" ((x86_reg)stride)
1525 1525
        : "%"REG_a, "%"REG_c
1526 1526
    );
1527 1527
#else
......
1591 1591
DEINT_CUBIC((%0, %1, 4) , (%%REGd, %1), (%%REGd, %1, 2), (%0, %1, 8) , (%%REGc))
1592 1592
DEINT_CUBIC((%%REGd, %1), (%0, %1, 8) , (%%REGd, %1, 4), (%%REGc)    , (%%REGc, %1, 2))
1593 1593

  
1594
        : : "r" (src), "r" ((long)stride)
1594
        : : "r" (src), "r" ((x86_reg)stride)
1595 1595
        : "%"REG_a, "%"REG_d, "%"REG_c
1596 1596
    );
1597 1597
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
1662 1662
DEINT_FF((%%REGd, %1), (%%REGd, %1, 2), (%0, %1, 8) , (%%REGd, %1, 4))
1663 1663

  
1664 1664
        "movq %%mm0, (%2)                       \n\t"
1665
        : : "r" (src), "r" ((long)stride), "r"(tmp)
1665
        : : "r" (src), "r" ((x86_reg)stride), "r"(tmp)
1666 1666
        : "%"REG_a, "%"REG_d
1667 1667
    );
1668 1668
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
1752 1752

  
1753 1753
        "movq %%mm0, (%2)                       \n\t"
1754 1754
        "movq %%mm1, (%3)                       \n\t"
1755
        : : "r" (src), "r" ((long)stride), "r"(tmp), "r"(tmp2)
1755
        : : "r" (src), "r" ((x86_reg)stride), "r"(tmp), "r"(tmp2)
1756 1756
        : "%"REG_a, "%"REG_d
1757 1757
    );
1758 1758
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
1840 1840
        "movq %%mm2, (%%"REG_d", %1, 2)         \n\t"
1841 1841
        "movq %%mm1, (%2)                       \n\t"
1842 1842

  
1843
        : : "r" (src), "r" ((long)stride), "r" (tmp)
1843
        : : "r" (src), "r" ((x86_reg)stride), "r" (tmp)
1844 1844
        : "%"REG_a, "%"REG_d
1845 1845
    );
1846 1846
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
1944 1944
        "movq %%mm2, (%%"REG_d", %1, 2)         \n\t"
1945 1945

  
1946 1946

  
1947
        : : "r" (src), "r" ((long)stride)
1947
        : : "r" (src), "r" ((x86_reg)stride)
1948 1948
        : "%"REG_a, "%"REG_d
1949 1949
    );
1950 1950

  
......
1986 1986
MEDIAN((%0, %1, 4) , (%%REGd)       , (%%REGd, %1))
1987 1987
MEDIAN((%%REGd, %1), (%%REGd, %1, 2), (%0, %1, 8))
1988 1988

  
1989
        : : "r" (src), "r" ((long)stride)
1989
        : : "r" (src), "r" ((x86_reg)stride)
1990 1990
        : "%"REG_a, "%"REG_d
1991 1991
    );
1992 1992
#endif //HAVE_MMX2
......
2093 2093
        "movd %%mm1, 116(%3)                    \n\t"
2094 2094

  
2095 2095

  
2096
        :: "r" (src), "r" ((long)srcStride), "r" (dst1), "r" (dst2)
2096
        :: "r" (src), "r" ((x86_reg)srcStride), "r" (dst1), "r" (dst2)
2097 2097
        : "%"REG_a
2098 2098
    );
2099 2099
}
......
2173 2173
        "psrlq $32, %%mm1                       \n\t"
2174 2174
        "movd %%mm1, 4(%%"REG_d", %1, 2)        \n\t"
2175 2175

  
2176
        :: "r" (dst), "r" ((long)dstStride), "r" (src)
2176
        :: "r" (dst), "r" ((x86_reg)dstStride), "r" (src)
2177 2177
        : "%"REG_a, "%"REG_d
2178 2178
    );
2179 2179
}
......
2476 2476

  
2477 2477
        "4:                                     \n\t"
2478 2478

  
2479
        :: "r" (src), "r" (tempBlurred), "r"((long)stride), "m" (tempBlurredPast)
2479
        :: "r" (src), "r" (tempBlurred), "r"((x86_reg)stride), "m" (tempBlurredPast)
2480 2480
        : "%"REG_a, "%"REG_d, "%"REG_c, "memory"
2481 2481
    );
2482 2482
#else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
......
2676 2676
        "movq %%mm6, %0                         \n\t"
2677 2677

  
2678 2678
        : "=m" (eq_mask), "=m" (dc_mask)
2679
        : "r" (src), "r" ((long)step), "m" (c->pQPb), "m"(c->ppMode.flatnessThreshold)
2679
        : "r" (src), "r" ((x86_reg)step), "m" (c->pQPb), "m"(c->ppMode.flatnessThreshold)
2680 2680
        : "%"REG_a
2681 2681
    );
2682 2682

  
2683 2683
    both_masks = dc_mask & eq_mask;
2684 2684

  
2685 2685
    if(both_masks){
2686
        long offset= -8*step;
2686
        x86_reg offset= -8*step;
2687 2687
        int64_t *temp_sums= sums;
2688 2688

  
2689 2689
        __asm__ volatile(
......
2820 2820
            "mov %4, %0                             \n\t" //FIXME
2821 2821

  
2822 2822
            : "+&r"(src)
2823
            : "r" ((long)step), "m" (c->pQPb), "r"(sums), "g"(src)
2823
            : "r" ((x86_reg)step), "m" (c->pQPb), "r"(sums), "g"(src)
2824 2824
        );
2825 2825

  
2826 2826
        src+= step; // src points to begin of the 8x8 Block
......
2857 2857
            " js 1b                                 \n\t"
2858 2858

  
2859 2859
            : "+r"(offset), "+r"(temp_sums)
2860
            : "r" ((long)step), "r"(src - offset), "m"(both_masks)
2860
            : "r" ((x86_reg)step), "r"(src - offset), "m"(both_masks)
2861 2861
        );
2862 2862
    }else
2863 2863
        src+= step; // src points to begin of the 8x8 Block
......
3092 3092
            "movq %%mm0, (%0, %1)                   \n\t"
3093 3093

  
3094 3094
            : "+r" (temp_src)
3095
            : "r" ((long)step), "m" (c->pQPb), "m"(eq_mask)
3095
            : "r" ((x86_reg)step), "m" (c->pQPb), "m"(eq_mask)
3096 3096
            : "%"REG_a, "%"REG_c
3097 3097
        );
3098 3098
    }
......
3193 3193
        : "0" (packedOffsetAndScale),
3194 3194
        "r"(src),
3195 3195
        "r"(dst),
3196
        "r" ((long)srcStride),
3197
        "r" ((long)dstStride)
3196
        "r" ((x86_reg)srcStride),
3197
        "r" ((x86_reg)dstStride)
3198 3198
        : "%"REG_d
3199 3199
    );
3200 3200
#else //HAVE_MMX
......
3226 3226

  
3227 3227
        : : "r" (src),
3228 3228
        "r" (dst),
3229
        "r" ((long)srcStride),
3230
        "r" ((long)dstStride)
3229
        "r" ((x86_reg)srcStride),
3230
        "r" ((x86_reg)dstStride)
3231 3231
        : "%"REG_a, "%"REG_d
3232 3232
    );
3233 3233
#else //HAVE_MMX
......
3251 3251
        "movq %%mm0, (%0, %1)           \n\t"
3252 3252
        "movq %%mm0, (%0, %1, 2)        \n\t"
3253 3253
        : "+r" (src)
3254
        : "r" ((long)-stride)
3254
        : "r" ((x86_reg)-stride)
3255 3255
    );
3256 3256
#else
3257 3257
    int i;
......
3406 3406
                "add %3, %%"REG_d"              \n\t"
3407 3407
                "prefetchnta 32(%%"REG_a", %0)  \n\t"
3408 3408
                "prefetcht0 32(%%"REG_d", %2)   \n\t"
3409
                :: "r" (srcBlock), "r" ((long)srcStride), "r" (dstBlock), "r" ((long)dstStride),
3410
                "g" ((long)x), "g" ((long)copyAhead)
3409
                :: "r" (srcBlock), "r" ((x86_reg)srcStride), "r" (dstBlock), "r" ((x86_reg)dstStride),
3410
                "g" ((x86_reg)x), "g" ((x86_reg)copyAhead)
3411 3411
                : "%"REG_a, "%"REG_d
3412 3412
            );
3413 3413

  
......
3542 3542
                "add %3, %%"REG_d"              \n\t"
3543 3543
                "prefetchnta 32(%%"REG_a", %0)  \n\t"
3544 3544
                "prefetcht0 32(%%"REG_d", %2)   \n\t"
3545
                :: "r" (srcBlock), "r" ((long)srcStride), "r" (dstBlock), "r" ((long)dstStride),
3546
                "g" ((long)x), "g" ((long)copyAhead)
3545
                :: "r" (srcBlock), "r" ((x86_reg)srcStride), "r" (dstBlock), "r" ((x86_reg)dstStride),
3546
                "g" ((x86_reg)x), "g" ((x86_reg)copyAhead)
3547 3547
                : "%"REG_a, "%"REG_d
3548 3548
            );
3549 3549

  

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