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ffmpeg / libavcodec / arm / dsputil_vfp.S @ a2fc0f6a

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/*
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 * Copyright (c) 2008 Siarhei Siamashka <ssvb@users.sourceforge.net>
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 *
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 * This file is part of FFmpeg.
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 *
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 * FFmpeg is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
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 *
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 * FFmpeg is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with FFmpeg; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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 */
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#include "config.h"
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#include "asm.S"
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        .fpu neon       @ required for gas to accept UAL syntax
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/*
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 * VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle
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 * throughput for almost all the instructions (except for double precision
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 * arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles
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 * for arithmetic operations. Scheduling code to avoid pipeline stalls is very
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 * important for performance. One more interesting feature is that VFP has
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 * independent load/store and arithmetics pipelines, so it is possible to make
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 * them work simultaneously and get more than 1 operation per cycle. Load/store
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 * pipeline can process 2 single precision floating point values per cycle and
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 * supports bulk loads and stores for large sets of registers. Arithmetic operations
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 * can be done on vectors, which allows to keep the arithmetics pipeline busy,
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 * while the processor may issue and execute other instructions. Detailed
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 * optimization manuals can be found at http://www.arm.com
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 */
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/**
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 * ARM VFP optimized implementation of 'vector_fmul_c' function.
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 * Assume that len is a positive number and is multiple of 8
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 */
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@ void ff_vector_fmul_vfp(float *dst, const float *src, int len)
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function ff_vector_fmul_vfp, export=1
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        vpush           {d8-d15}
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        mov             r3,  r0
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        fmrx            r12, fpscr
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        orr             r12, r12, #(3 << 16) /* set vector size to 4 */
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        fmxr            fpscr, r12
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        vldmia          r3!, {s0-s3}
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        vldmia          r1!, {s8-s11}
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        vldmia          r3!, {s4-s7}
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        vldmia          r1!, {s12-s15}
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        vmul.f32        s8,  s0,  s8
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1:
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        subs            r2,  r2,  #16
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        vmul.f32        s12, s4,  s12
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        vldmiage        r3!, {s16-s19}
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        vldmiage        r1!, {s24-s27}
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        vldmiage        r3!, {s20-s23}
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        vldmiage        r1!, {s28-s31}
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        vmulge.f32      s24, s16, s24
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        vstmia          r0!, {s8-s11}
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        vstmia          r0!, {s12-s15}
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        vmulge.f32      s28, s20, s28
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        vldmiagt        r3!, {s0-s3}
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        vldmiagt        r1!, {s8-s11}
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        vldmiagt        r3!, {s4-s7}
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        vldmiagt        r1!, {s12-s15}
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        vmulge.f32      s8,  s0,  s8
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        vstmiage        r0!, {s24-s27}
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        vstmiage        r0!, {s28-s31}
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        bgt             1b
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        bic             r12, r12, #(7 << 16) /* set vector size back to 1 */
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        fmxr            fpscr, r12
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        vpop            {d8-d15}
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        bx              lr
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        .endfunc
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/**
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 * ARM VFP optimized implementation of 'vector_fmul_reverse_c' function.
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 * Assume that len is a positive number and is multiple of 8
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 */
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@ void ff_vector_fmul_reverse_vfp(float *dst, const float *src0,
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@                                 const float *src1, int len)
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function ff_vector_fmul_reverse_vfp, export=1
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        vpush           {d8-d15}
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        add             r2,  r2,  r3, lsl #2
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        vldmdb          r2!, {s0-s3}
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        vldmia          r1!, {s8-s11}
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        vldmdb          r2!, {s4-s7}
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        vldmia          r1!, {s12-s15}
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        vmul.f32        s8,  s3,  s8
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        vmul.f32        s9,  s2,  s9
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        vmul.f32        s10, s1,  s10
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        vmul.f32        s11, s0,  s11
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        subs            r3,  r3,  #16
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        vldmdbge        r2!, {s16-s19}
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        vmul.f32        s12, s7,  s12
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        vldmiage        r1!, {s24-s27}
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        vmul.f32        s13, s6,  s13
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        vldmdbge        r2!, {s20-s23}
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        vmul.f32        s14, s5,  s14
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        vldmiage        r1!, {s28-s31}
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        vmul.f32        s15, s4,  s15
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        vmulge.f32      s24, s19, s24
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        vldmdbgt        r2!, {s0-s3}
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        vmulge.f32      s25, s18, s25
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        vstmia          r0!, {s8-s13}
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        vmulge.f32      s26, s17, s26
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        vldmiagt        r1!, {s8-s11}
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        vmulge.f32      s27, s16, s27
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        vmulge.f32      s28, s23, s28
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        vldmdbgt        r2!, {s4-s7}
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        vmulge.f32      s29, s22, s29
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        vstmia          r0!, {s14-s15}
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        vmulge.f32      s30, s21, s30
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        vmulge.f32      s31, s20, s31
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        vmulge.f32      s8,  s3,  s8
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        vldmiagt        r1!, {s12-s15}
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        vmulge.f32      s9,  s2,  s9
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        vmulge.f32      s10, s1,  s10
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        vstmiage        r0!, {s24-s27}
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        vmulge.f32      s11, s0,  s11
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        vstmiage        r0!, {s28-s31}
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        bgt             1b
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        vpop            {d8-d15}
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        bx              lr
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        .endfunc
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#ifdef HAVE_ARMV6
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/**
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 * ARM VFP optimized float to int16 conversion.
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 * Assume that len is a positive number and is multiple of 8, destination
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 * buffer is at least 4 bytes aligned (8 bytes alignment is better for
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 * performance), little endian byte sex
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 */
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@ void ff_float_to_int16_vfp(int16_t *dst, const float *src, int len)
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function ff_float_to_int16_vfp, export=1
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        push            {r4-r8,lr}
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        vpush           {d8-d11}
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        vldmia          r1!, {s16-s23}
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        vcvt.s32.f32    s0,  s16
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        vcvt.s32.f32    s1,  s17
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        vcvt.s32.f32    s2,  s18
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        vcvt.s32.f32    s3,  s19
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        vcvt.s32.f32    s4,  s20
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        vcvt.s32.f32    s5,  s21
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        vcvt.s32.f32    s6,  s22
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        vcvt.s32.f32    s7,  s23
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        subs            r2,  r2,  #8
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        vmov            r3,  r4,  s0, s1
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        vmov            r5,  r6,  s2, s3
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        vmov            r7,  r8,  s4, s5
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        vmov            ip,  lr,  s6, s7
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        vldmiagt        r1!, {s16-s23}
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        ssat            r4,  #16, r4
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        ssat            r3,  #16, r3
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        ssat            r6,  #16, r6
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        ssat            r5,  #16, r5
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        pkhbt           r3,  r3,  r4, lsl #16
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        pkhbt           r4,  r5,  r6, lsl #16
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        vcvtgt.s32.f32  s0,  s16
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        vcvtgt.s32.f32  s1,  s17
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        vcvtgt.s32.f32  s2,  s18
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        vcvtgt.s32.f32  s3,  s19
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        vcvtgt.s32.f32  s4,  s20
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        vcvtgt.s32.f32  s5,  s21
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        vcvtgt.s32.f32  s6,  s22
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        vcvtgt.s32.f32  s7,  s23
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        ssat            r8,  #16, r8
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        ssat            r7,  #16, r7
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        ssat            lr,  #16, lr
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        ssat            ip,  #16, ip
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        pkhbt           r5,  r7,  r8, lsl #16
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        pkhbt           r6,  ip,  lr, lsl #16
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        stmia           r0!, {r3-r6}
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        bgt             1b
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        vpop            {d8-d11}
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        pop             {r4-r8,pc}
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        .endfunc
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#endif