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/*
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 * Copyright (c) 2002 Brian Foley
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 * Copyright (c) 2002 Dieter Shirley
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "../dsputil.h"
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#include "dsputil_ppc.h"
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#ifdef HAVE_ALTIVEC
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#include "dsputil_altivec.h"
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#endif
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extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block);
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extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block);
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int mm_flags = 0;
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int mm_support(void)
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{
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    int result = 0;
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#if HAVE_ALTIVEC
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    if (has_altivec()) {
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        result |= MM_ALTIVEC;
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    }
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#endif /* result */
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    return result;
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}
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#ifdef POWERPC_PERFORMANCE_REPORT
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unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total];
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/* list below must match enum in dsputil_ppc.h */
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static unsigned char* perfname[] = {
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  "fft_calc_altivec",
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  "gmc1_altivec",
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  "dct_unquantize_h263_altivec",
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  "idct_add_altivec",
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  "idct_put_altivec",
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  "put_pixels16_altivec",
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  "avg_pixels16_altivec",
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  "avg_pixels8_altivec",
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  "put_pixels8_xy2_altivec",
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  "put_no_rnd_pixels8_xy2_altivec",
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  "put_pixels16_xy2_altivec",
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  "put_no_rnd_pixels16_xy2_altivec",
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  "clear_blocks_dcbz32_ppc",
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  "clear_blocks_dcbz128_ppc"
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};
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#include <stdio.h>
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#endif
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#ifdef POWERPC_PERFORMANCE_REPORT
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void powerpc_display_perf_report(void)
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{
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  int i, j;
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  fprintf(stderr, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
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  for(i = 0 ; i < powerpc_perf_total ; i++)
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  {
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    for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++)
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      {
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        if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0)
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          fprintf(stderr,
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                  " Function \"%s\" (pmc%d):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
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                  perfname[i],
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                  j+1,
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                  perfdata[j][i][powerpc_data_min],
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                  perfdata[j][i][powerpc_data_max],
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                  (double)perfdata[j][i][powerpc_data_sum] /
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                  (double)perfdata[j][i][powerpc_data_num],
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                  perfdata[j][i][powerpc_data_num]);
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      }
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  }
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}
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#endif /* POWERPC_PERFORMANCE_REPORT */
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/* ***** WARNING ***** WARNING ***** WARNING ***** */
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/*
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  clear_blocks_dcbz32_ppc will not work properly
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  on PowerPC processors with a cache line size
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  not equal to 32 bytes.
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  Fortunately all processor used by Apple up to
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  at least the 7450 (aka second generation G4)
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  use 32 bytes cache line.
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  This is due to the use of the 'dcbz' instruction.
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  It simply clear to zero a single cache line,
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  so you need to know the cache line size to use it !
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  It's absurd, but it's fast...
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  update 24/06/2003 : Apple released yesterday the G5,
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  with a PPC970. cache line size : 128 bytes. Oups.
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  The semantic of dcbz was changed, it always clear
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  32 bytes. so the function below will work, but will
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  be slow. So I fixed check_dcbz_effect to use dcbzl,
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  which is defined to clear a cache line (as dcbz before).
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  So we still can distinguish, and use dcbz (32 bytes)
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  or dcbzl (one cache line) as required.
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  see <http://developer.apple.com/technotes/tn/tn2087.html>
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  and <http://developer.apple.com/technotes/tn/tn2086.html>
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*/
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void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
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{
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POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1);
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    register int misal = ((unsigned long)blocks & 0x00000010);
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    register int i = 0;
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POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
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#if 1
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    if (misal) {
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      ((unsigned long*)blocks)[0] = 0L;
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      ((unsigned long*)blocks)[1] = 0L;
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      ((unsigned long*)blocks)[2] = 0L;
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      ((unsigned long*)blocks)[3] = 0L;
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      i += 16;
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    }
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    for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) {
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      asm volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
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    }
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    if (misal) {
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      ((unsigned long*)blocks)[188] = 0L;
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      ((unsigned long*)blocks)[189] = 0L;
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      ((unsigned long*)blocks)[190] = 0L;
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      ((unsigned long*)blocks)[191] = 0L;
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      i += 16;
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    }
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#else
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    memset(blocks, 0, sizeof(DCTELEM)*6*64);
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#endif
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POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
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}
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/* same as above, when dcbzl clear a whole 128B cache line
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   i.e. the PPC970 aka G5 */
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#ifndef NO_DCBZL
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void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
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{
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POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1);
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    register int misal = ((unsigned long)blocks & 0x0000007f);
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    register int i = 0;
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POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
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#if 1
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 if (misal) {
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   // we could probably also optimize this case,
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   // but there's not much point as the machines
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   // aren't available yet (2003-06-26)
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      memset(blocks, 0, sizeof(DCTELEM)*6*64);
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    }
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    else
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      for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
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        asm volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
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      }
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#else
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    memset(blocks, 0, sizeof(DCTELEM)*6*64);
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#endif
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POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
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}
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#else
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void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
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{
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  memset(blocks, 0, sizeof(DCTELEM)*6*64);
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}
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#endif
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#ifndef NO_DCBZL
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/* check dcbz report how many bytes are set to 0 by dcbz */
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/* update 24/06/2003 : replace dcbz by dcbzl to get
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   the intended effect (Apple "fixed" dcbz)
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   unfortunately this cannot be used unless the assembler
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   knows about dcbzl ... */
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long check_dcbzl_effect(void)
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{
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  register char *fakedata = (char*)av_malloc(1024);
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  register char *fakedata_middle;
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  register long zero = 0;
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  register long i = 0;
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  long count = 0;
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  if (!fakedata)
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  {
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    return 0L;
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  }
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  fakedata_middle = (fakedata + 512);
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  memset(fakedata, 0xFF, 1024);
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  /* below the constraint "b" seems to mean "Address base register"
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     in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
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  asm volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
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  for (i = 0; i < 1024 ; i ++)
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  {
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    if (fakedata[i] == (char)0)
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      count++;
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  }
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  av_free(fakedata);
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  return count;
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}
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#else
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long check_dcbzl_effect(void)
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{
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  return 0;
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}
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#endif
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void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
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{
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    // Common optimizations whether Altivec is available or not
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  switch (check_dcbzl_effect()) {
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  case 32:
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    c->clear_blocks = clear_blocks_dcbz32_ppc;
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    break;
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  case 128:
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    c->clear_blocks = clear_blocks_dcbz128_ppc;
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    break;
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  default:
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    break;
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  }
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#if HAVE_ALTIVEC
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    if (has_altivec()) {
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        mm_flags |= MM_ALTIVEC;
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        // Altivec specific optimisations
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        c->pix_abs16x16_x2 = pix_abs16x16_x2_altivec;
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        c->pix_abs16x16_y2 = pix_abs16x16_y2_altivec;
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        c->pix_abs16x16_xy2 = pix_abs16x16_xy2_altivec;
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        c->pix_abs16x16 = pix_abs16x16_altivec;
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        c->pix_abs8x8 = pix_abs8x8_altivec;
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        c->sad[0]= sad16x16_altivec;
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        c->sad[1]= sad8x8_altivec;
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        c->pix_norm1 = pix_norm1_altivec;
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        c->sse[1]= sse8_altivec;
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        c->sse[0]= sse16_altivec;
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        c->pix_sum = pix_sum_altivec;
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        c->diff_pixels = diff_pixels_altivec;
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        c->get_pixels = get_pixels_altivec;
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// next one disabled as it's untested.
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#if 0
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        c->add_bytes= add_bytes_altivec;
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#endif /* 0 */
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        c->put_pixels_tab[0][0] = put_pixels16_altivec;
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        /* the tow functions do the same thing, so use the same code */
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        c->put_no_rnd_pixels_tab[0][0] = put_pixels16_altivec;
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        c->avg_pixels_tab[0][0] = avg_pixels16_altivec;
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// next one disabled as it's untested.
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#if 0
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        c->avg_pixels_tab[1][0] = avg_pixels8_altivec;
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#endif /* 0 */
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        c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec;
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        c->put_no_rnd_pixels_tab[1][3] = put_no_rnd_pixels8_xy2_altivec;
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        c->put_pixels_tab[0][3] = put_pixels16_xy2_altivec;
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        c->put_no_rnd_pixels_tab[0][3] = put_no_rnd_pixels16_xy2_altivec;
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        c->gmc1 = gmc1_altivec;
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        if ((avctx->idct_algo == FF_IDCT_AUTO) ||
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                (avctx->idct_algo == FF_IDCT_ALTIVEC))
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        {
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            c->idct_put = idct_put_altivec;
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            c->idct_add = idct_add_altivec;
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#ifndef ALTIVEC_USE_REFERENCE_C_CODE
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            c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
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#else /* ALTIVEC_USE_REFERENCE_C_CODE */
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            c->idct_permutation_type = FF_NO_IDCT_PERM;
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#endif /* ALTIVEC_USE_REFERENCE_C_CODE */
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        }
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#ifdef POWERPC_PERFORMANCE_REPORT
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        {
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          int i, j;
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          for (i = 0 ; i < powerpc_perf_total ; i++)
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          {
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            for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++)
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              {
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                perfdata[j][i][powerpc_data_min] = (unsigned long long)0xFFFFFFFFFFFFFFFF;
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                perfdata[j][i][powerpc_data_max] = (unsigned long long)0x0000000000000000;
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                perfdata[j][i][powerpc_data_sum] = (unsigned long long)0x0000000000000000;
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                perfdata[j][i][powerpc_data_num] = (unsigned long long)0x0000000000000000;
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              }
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          }
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        }
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#endif /* POWERPC_PERFORMANCE_REPORT */
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    } else
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#endif /* HAVE_ALTIVEC */
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    {
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        // Non-AltiVec PPC optimisations
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        // ... pending ...
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    }
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}