Revision e42a152b libavcodec/i386/cputest.c
libavcodec/i386/cputest.c  

27  27 
{ 
28  28 
int rval = 0; 
29  29 
int eax, ebx, ecx, edx; 
30 
int max_std_level, max_ext_level, std_caps=0, ext_caps=0; 

30  31 
long a, c; 
31  32 

32  33 
__asm__ __volatile__ ( 
...  ...  
52  53 

53  54 
if (a == c) 
54  55 
return 0; /* CPUID not supported */ 
55 


56 
cpuid(0, eax, ebx, ecx, edx); 

57  56  
58 
if (ebx == 0x756e6547 && 

59 
edx == 0x49656e69 && 

60 
ecx == 0x6c65746e) { 

61 


62 
/* intel */ 

63 
inteltest: 

64 
cpuid(1, eax, ebx, ecx, edx); 

65 
if ((edx & 0x00800000) == 0) 

66 
return 0; 

67 
rval = MM_MMX; 

68 
if (edx & 0x02000000) 

57 
cpuid(0, max_std_level, ebx, ecx, edx); 

58  
59 
if(max_std_level >= 1){ 

60 
cpuid(1, eax, ebx, ecx, std_caps); 

61 
if (std_caps & (1<<23)) 

62 
rval = MM_MMX; 

63 
if (std_caps & (1<<25)) 

69  64 
rval = MM_MMXEXT  MM_SSE; 
70 
if (edx & 0x04000000)


65 
if (std_caps & (1<<26))


71  66 
rval = MM_SSE2; 
72 
return rval; 

73 
} else if (ebx == 0x68747541 && 

67 
} 

68  
69 
cpuid(0x80000000, max_ext_level, ebx, ecx, edx); 

70  
71 
if(max_ext_level >= 0x80000001){ 

72 
cpuid(0x80000001, eax, ebx, ecx, ext_caps); 

73 
if (ext_caps & (1<<31)) 

74 
rval = MM_3DNOW; 

75 
if (ext_caps & (1<<30)) 

76 
rval = MM_3DNOWEXT; 

77 
if (ext_caps & (1<<23)) 

78 
rval = MM_MMX; 

79 
} 

80  
81 
cpuid(0, eax, ebx, ecx, edx); 

82 
if ( ebx == 0x68747541 && 

74  83 
edx == 0x69746e65 && 
75  84 
ecx == 0x444d4163) { 
76  85 
/* AMD */ 
77 
cpuid(0x80000000, eax, ebx, ecx, edx); 

78 
if ((unsigned)eax < 0x80000001) 

79 
goto inteltest; 

80 
cpuid(0x80000001, eax, ebx, ecx, edx); 

81 
if ((edx & 0x00800000) == 0) 

82 
return 0; 

83 
rval = MM_MMX; 

84 
if (edx & 0x80000000) 

85 
rval = MM_3DNOW; 

86 
if (edx & 0x00400000) 

86 
if(ext_caps & (1<<22)) 

87  87 
rval = MM_MMXEXT; 
88 
goto inteltest; 

89  88 
} else if (ebx == 0x746e6543 && 
90  89 
edx == 0x48727561 && 
91  90 
ecx == 0x736c7561) { /* "CentaurHauls" */ 
92  91 
/* VIA C3 */ 
93 
cpuid(0x80000000, eax, ebx, ecx, edx); 

94 
if ((unsigned)eax < 0x80000001) 

95 
goto inteltest; 

96 
cpuid(0x80000001, eax, ebx, ecx, edx); 

97 
rval = 0; 

98 
if( edx & ( 1 << 31) ) 

99 
rval = MM_3DNOW; 

100 
if( edx & ( 1 << 23) ) 

101 
rval = MM_MMX; 

102 
if( edx & ( 1 << 24) ) 

92 
if(ext_caps & (1<<24)) 

103  93 
rval = MM_MMXEXT; 
104 
if(rval==0) 

105 
goto inteltest; 

106 
return rval; 

107  94 
} else if (ebx == 0x69727943 && 
108  95 
edx == 0x736e4978 && 
109  96 
ecx == 0x64616574) { 
...  ...  
116  103 
According to the table, the only CPU which supports level 
117  104 
2 is also the only one which supports extended CPUID levels. 
118  105 
*/ 
119 
if (eax != 2) 

120 
goto inteltest; 

121 
cpuid(0x80000001, eax, ebx, ecx, edx); 

122 
if ((eax & 0x00800000) == 0) 

123 
return 0; 

124 
rval = MM_MMX; 

125 
if (eax & 0x01000000) 

106 
if (eax < 2) 

107 
return rval; 

108 
if (ext_caps & (1<<24)) 

126  109 
rval = MM_MMXEXT; 
127 
return rval; 

128 
} else if (ebx == 0x756e6547 && 

129 
edx == 0x54656e69 && 

130 
ecx == 0x3638784d) { 

131 
/* Tranmeta Crusoe */ 

132 
cpuid(0x80000000, eax, ebx, ecx, edx); 

133 
if ((unsigned)eax < 0x80000001) 

134 
return 0; 

135 
cpuid(0x80000001, eax, ebx, ecx, edx); 

136 
if ((edx & 0x00800000) == 0) 

137 
return 0; 

138 
return MM_MMX; 

139 
} else { 

140 
return 0; 

141  110 
} 
111 
#if 0 

112 
av_log(NULL, AV_LOG_DEBUG, "%s%s%s%s%s%s\n", 

113 
(rval&MM_MMX) ? "MMX ":"", 

114 
(rval&MM_MMXEXT) ? "MMX2 ":"", 

115 
(rval&MM_SSE) ? "SSE ":"", 

116 
(rval&MM_SSE2) ? "SSE2 ":"", 

117 
(rval&MM_3DNOW) ? "3DNow ":"", 

118 
(rval&MM_3DNOWEXT) ? "3DNowExt ":""); 

119 
#endif 

120 
return rval; 

142  121 
} 
143  122  
144  123 
#ifdef __TEST__ 
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